ADPD4100 datasheet(31/101 Pages) AD

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Data Sheet

ADPD4100/ADPD4101

Rev. 0 | Page 31 of 101

Improving SNR Using Integrator Chopping

The last stage in the ADPD4100/ADPD4101 datapath is a

charge integrator. The integrator uses an on and off integration

sequence, synchronized to the emitted light pulse, which acts as

an additional high-pass filter to remove offsets, drifts, and low

frequency noise from the previous stages. However, the

integrating amplifier can itself introduce low frequency signal

content. The ADPD4100/ADPD4101 have a mode that enables

additional chopping in the digital domain to remove this signal.

Chopping is achieved by using an even number of pulses per

sample and inverting the integration sequence for half of those

sequences. When the calculation is performed to combine the

digitized result of each of the pulses of the sample, the sequences

with an inverted integrator sequence are subtracted and the

sequences with a normal integrator sequence are added. An

example diagram of the integrator chopping sequence is shown

in Figure 36.

The result of chopping is that any low frequency signal contribu-

tion from the integrator is eliminated, leaving only the

integrated signal and resulting in higher SNR, especially at

higher numbers of pulses and at lower TIA gains where the

noise contribution of the integrator becomes more pronounced.

Digital chopping is enabled using the registers and bits detailed

in Table 19. The bits define the chopping operation for the first

four pulses. This 4-bit sequence is then repeated for all

subsequent sequence of four pulses. In Figure 36, a sequence is

shown where the second and fourth pulses are inverted while the

first and third pulses remain in the default polarity (noninverted).

This configuration is achieved by setting the REVERSE_INTEG_x

bits = 0xA to reverse the integration sequence for the second and

fourth pulses. To complete the operation, the math must be

adjusted by setting the SUBTRACT_x bits = 0xA. An even

number of pulses must be used with integrator chop mode.

Because integrator chopping eliminates the low frequency noise

contribution from the integrator, it is recommended to always

keep integrator chop mode enabled in continuous connect

mode to achieve optimal SNR performance.

When using integrator chopping, the ADC offset bits,

CH1_ADC_ADJUST_x and CH2_ADC_ADJUST_x, must be

set to 0, because when the math is adjusted to subtract inverted

integration sequences while default integration sequences are

added, any digital offsets at the output of the ADC are automati-

cally eliminated. Integrator chop mode also eliminates the need

to manually null the ADC offsets at startup in a typical application.

Note that the elimination of the offset using integrator chop

mode can clip at least half of the noise signal when no input

signal is present, which makes it difficult to measure the noise

floor during characterization of the system. There are three

options for performing noise floor characterization of the system.

•

Integrator chop mode disabled.

•

Integrator chop mode enabled but with a minimal signal

present at the input, which increases the noise floor

enough such that it is no longer clipped.

•

Setting the ZERO_ADJUST_x bit = 1, which adds 2048 codes

to the end result.

LED

–

INTEGRATOR

SEQUENCE

ADC

BPF OUTPUT

–

PULSE 1

PULSE 2

PULSE 3

PULSE 4

Figure 36. Diagram of Integrator Chopping Sequence

Table 19. Register Settings for Integrator Chop Mode

Group

Time Slot A

Address1

Bit Field Name

Description

Integrator

Chop Mode

0x010D, Bits[7:4]

SUBTRACT_x

Four-pulse subtract pattern. Set to 1 to negate the math operation in the

matching position in a group of four pulses. The LSB maps to the first pulse.

0x010D, Bits[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set to 1 to reverse the integrator positive

and negative pulse order in the matching position in a group of four pulses. The

LSB maps to the first pulse.

This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x010D is the location for

SUBTRACT_A. For Time Slot B, this register is at Address 0x012D, For Time Slot C, this register is at Address 0x014D. For Time Slot D, this register is at Address 0x016D,

and so on.

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