ADPD4100 datasheet(82/101 Pages) AD

82 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 82 of 101

Addr

Name

Bits

Bit Name

Description

Reset Access1

0x001E FIFO_STATUS_BYTES [15:9]

Reserved

Reserved.

0x0

ENA_STAT_TCX

Enable Channel 1 and Channel 2 TIA ceiling detection

interrupt status byte for Time Slot I through Time Slot L.

This byte contains the interrupt status for the Channel 1

and Channel 2 interrupts for Time Slot I through Time Slot L.

0x0

ENA_STAT_TC2

Enable Channel 2 TIA ceiling detection interrupt status

byte for Time Slot A through Time Slot H. This byte

contains the interrupt status for the Channel 2 and

Channel 2 interrupts for Time Slot A through Time Slot H.

0x0

ENA_STAT_TC1

Enable Channel 1 TIA ceiling detection interrupt status

byte for Time Slot A through Time Slot H. This byte

contains the interrupt status for the Channel 1 and

Channel 2 interrupts for Time Slot A through Time Slot H.

0x0

ENA_STAT_LX

Enable Level 0 and Level 1 interrupt status byte for

Time Slot I through Time Slot L. This byte contains the

interrupt status for the Level 0 and Level 1 interrupts for

Time Slot I through Time Slot L.

0x0

R/W

ENA_STAT_L1

Enable Level 1 interrupt status byte for Time Slot A

through Time Slot H. This byte contains the interrupt

status for the Level 1 interrupts for Time Slot A through

Time Slot H.

0x0

R/W

ENA_STAT_L0

Enable Level 0 interrupt status byte for Time Slot A

through Time Slot H. This byte contains the interrupt

status for Level Interrupt 0 for Time Slot A through Time

Slot H.

0x0

R/W

ENA_STAT_D2

Enable data interrupt status byte for Time Slot I through

Time Slot L. This byte contains the data interrupt status

for Time Slot I through Time Slot L.

0x0

R/W

ENA_STAT_D1

Enable data interrupt status byte for Time Slot A through

Time Slot H. This byte is the data interrupt status for Time

Slot A through Time Slot H.

0x0

R/W

ENA_STAT_SUM

Enable status summary byte. When enabled, write a

status byte containing the summary pattern to the FIFO

following the last enabled time slot data.

0x0

R/W

R/W1C means write 1 to clear.

THRESHOLD SETUP AND CONTROL REGISTERS

Table 32. Threshold Setup and Control Register Details

Addr

Name

Bits

Bit Name

Description

Reset Access

0x0006 FIFO_TH

[15:10] Reserved

Reserved.

0x00

[9:0]

FIFO_TH

FIFO interrupt generation threshold. Generate FIFO interrupt

during a FIFO write when the number of bytes in the FIFO exceeds

this value. The FIFO is 512 bytes. Therefore, the maximum value for

FIFO_TH is 0x1FF.

0x000 R/W

0x0115 THRESH_CFG_A [15:8]

Reserved

Reserved.

0x0

0x0135 THRESH_CFG_B 7

THRESH1_CHAN_x Select channel for Level 1 interrupt.

0x0

R/W

0x0155 THRESH_CFG_C

0: use Channel 1.

0x0175 THRESH_CFG_D

1: use Channel 2.

0x0195 THRESH_CFG_E 6

THRESH1_DIR_x

Direction of comparison for Level 1 interrupt.

0x0

R/W

0x01B5 THRESH_CFG_F

0: set when below Level 1 interrupt threshold.

0x01D5 THRESH_CFG_G

1: set when above Level 1 interrupt threshold.

0x01F5 THRESH_CFG_H [5:4]

THRESH1_TYPE_x

Type of comparison for Level 1 interrupt.

0x0

R/W

0x0215 THRESH_CFG_I

0: off (no comparison).

0x0235 THRESH_CFG_J

1: compare to signal.

0x0255 THRESH_CFG_K

10: compare to dark.

0x0275 THRESH_CFG_L

11: reserved.

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