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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 122 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 122 Page - Texas Instruments |
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122 / 157 page  122 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000] Figure 6-78. MISC_BITS Register Format B7 B6 B5 B4 B3 B2 B1 B0 V13_PIN_OVR MV13EN V6_PIN_OVR MV6EN msLP_S3ZPG msLP_SUSZP G BC_ACOK_EN V13DISCHG 0 0 0 0 0 0 1 0 RW RW RW RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-59. MISC_BITS Register Field Descriptions Bit Field Type Reset Description 7 V13_PIN_OVR RW 0 V13 ENABLE PIN Over Ride 0: V13 is OFF if MV13EN is '1' 1: V13 is ON if MV13EN is '1' 6 MV13EN RW 0 V13 Enable Pin Mask 0: DDR_VT_CTRL Pin controls V13 1: V13_EN_PIN Bit [Bit(3)] controls V13 5 V6_PIN_OVR RW 0 V6 ENABLE PIN Over Ride 0: V6 Pin controls V6 1: V6 is ON if VREN PIN MASK = '0' 4 MV6EN RW 1 V6 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 3 msLP_S3ZPG RW 0 SLP_S3Z is part of the power good tree 0: SLP_S3Z is part of Power Good Tree 1: SLP_S3Z is masked and set to 1 (not part of the Power Good tree) 2 msLP_SUSZPG RW 0 SLP_SUSZ is part of the power good tree 0: SLP_SUSZ is part of Power Good Tree 1: SLP_SUSZ is masked and set to 1 (not part of the Power Good tree) 1 BC_ACOK_EN RW 1 Enables BC_ACOK output out of LVA pin. The in put is ACOK pin, instead of ENLVA pin. 0: LVA pin is not BC_ACOK, and ENLVA is the input for LVA output, behaving as a general purpose level-shifter. 1: LVA pin is BC_ACOK, and ACOK is the input, and ENLVA is not functional. BC_ACOK is a level-shifted version of ACOK. 0 V13DISCHG RW 0 V0.6DX discharge resistance (V13) 0: No discharge 1: 100 Ω |
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