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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R68MS 데이터시트(PDF) 123 Page - Texas Instruments |
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PIFE32251B-R68MS 데이터시트(HTML) 123 Page - Texas Instruments |
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123 / 157 page  123 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110] Figure 6-79. STDBY_CTRL Register Format B7 B6 B5 B4 B3 B2 B1 B0 RESERVED_S TDBY_CTRL[4] RESERVED_S TDBY_CTRL[3] RESERVED_S TDBY_CTRL[2] RESERVED_S TDBY_CTRL[1] RESERVED_S TDBY_CTRL[0] EN_VCOMP_1 0U VCOMPEN QLSLPS0_ACT IVE 1 1 1 1 1 1 1 0 R R R R R RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-60. STDBY_CTRL Register Field Descriptions Bit Field Type Reset Description 7:3 RESERVED_STDBY_CTRL[4:0] R 11111 Read Always Returns '1' 2 EN_VCOMP_10U RW 1 VCOMP Current Source Control bit: 0: Disable 1: Enable 1 VCOMPEN RW 1 VCOMP Enable Control bit: 0: Disable 1: Enable 0 QLSLPS0_ACTIVE RW 0 SLP_S0 & DDR_VTT_CTRL Detect logic Control 0: Normal Operation DELAY_ALL_SYS_PG is used in QSTANDBY# (SLP_S0#) 1: DELAY_ALL_SYS_PG is ignored for QSTANDBY# (SLP_S0#) |
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