 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PIFE32251B-R68MS 데이터시트(PDF) 138 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
PIFE32251B-R68MS 데이터시트(HTML) 138 Page - Texas Instruments |
|
|
138 / 157 page  FROM EC VDC LEGEND TTL = TTL LEVEL INPUT BUFFER 3L = 3 LEVEL (HI/LO/HI-Z) INPUT BUFFER PP = PUSH-PULL OUTPUT BUFFER PPB = PUSH PULL OUTPUT BUFFER WITH HI-Z MODE (TEST ONLY) OD = OPEN DRAIN OUTPUT BUFFER TR = PUSH-PULL WITH CONTROLLED Tr OD/PP = OPEN-DRAIN OR PUSH PULL AGND PGNDVR3 AGND PGNDVR2 PGNDVR3 GROUND PLANE PGNDVR4 PGNDVR5 PGNDVR1 VDC VDC AGND VDC AGND V5ADS3 V12U PGNDLDO1 AGND V33A_DSW VDC V100A PGNDLDO1 AGND V33A_DSW V18A V100S V085A VCCIO(V0975) VCCIOLSW VCCIOLSW VCCIO(V0975) V1.8S_PG V33S V33APCH V33APCHLSW V33APCHLSW V18S V33APCH_PG V18U25ULSW V100S_PG V33APCH V18U25U V33S V100S V5ADS3_PG V5ADS3_PG SLP_S4Z VR1_PG SLP_S3Z V33APCH_PG SLP_SUSZ SLP_S4Z DDR_VTT_CTRL V18S V18U25U V18U25ULSW SLP_S3Z SLP_S3Z SLP_S3Z VLDO3 VLDO5 VLDO3 V33ADSW_PG V18A_PG VLDO5 VLDO5 VLDO3 VLDO5 VLDO5 V12U_PG V18A_EN/ DPWROK PGNDVR4 PGNDVR5 PGNDVR1 PGNDVR2 V12U_PG & V100S_PG DDRID VOLUME #1 Application Block Diagram: V12(V085A) = No Load Sw, V11 (V1.00A) = No Load Sw SLP_S0Z LS_OUTB V9,V4,V33S PGOOD DO NOT HAVE PINS! SLP_SUSZ TH_HOTZ V33A_DSW V33A_DSW BCACOK V33A_DSW V100S V5A_DS3 V5ADS3_PG EC VDC V33A_DSW V100S_PG V12U_PG V33A_DSW (EC_VCC) THERMs All Pullup Resistors 100kohm, unless noted 50ohm Rpull-up Shared with V12U_PG V33A_DSW Rpull-up Shared with V100S_PG LDO3 LS_INB LS_INC LS_OUTC COMPOUT_C COMPEN_C COMPIN_C V33A_DSW VR2 Converter Vout range 1.76v-1.85v Vout 1.8V 2A max SWVR3 PGNDVR3 VBSTVR3 FBVR3P DRVHVR3 DRVLVR3 PG PG AGND [4] UVLO OTP DIGCORE I2C AND REGFILE VDDIO [2X] DFT AND AMUX PGA PGB PGC PGD SWVR5 PGNDVR5 VBSTVR5 FBVR5P DRVHVR5 DRVLVR5 ILIMVR5HS VINVR5 EN/ PGOOD LOGIC LDO1 SINK/SRC LDO V0.6DX/0.675DX /0.55DX Vout= (VR4)/2 1A max EN VOUTLDO1[2X] FBLDO1 VINDLO1S PGNDLDO1[2X] DDR_VTT_CTRL VINLDO1[2X] EN LOGIC BACKUP BATTERY SELECTOR VBATTBKUP V3P3A_RTC RTC DIG DIETEMP FBVR3N VR4 Controller Vout Range 1.056V- 1.391V Vout 1.2V/ 1.35V/1.1V DRVLVR4 VBSTVR4 FBVR4P SWVR4 PGNDVR4 ILIMVR4 VREGVR4 FBVR4N VINLDO3 LDO5V VREF1V25 EN3V3SW LDO3V REFSYS VIN EN VSET EN VSET EN VSET EN/ PGOOD LOGIC PG EN VSET VDDIO 3 L TEMP_ALERTZ ENVR3 ENVR4 FBVR5N ENVR5 OD VDDPG OD/PP PGVR1 EN/ PGOOD LOGIC SWVR1 PGNDVR1 VBSTVR1 FBVR1P DRVHVR1 DRVLVR1 PG ILIMVR1 VREGVR1 EN VSET FBVR1N ENVR1 VDDIO PGVR5 EN/ PGOOD LOGIC EN/ PGOOD LOGIC VDDIO TTL VDDIO TTL VDDIO TTL ENVR2 VDDIO TTL VDDIO TTL SEQ + INTEL AND OEM LOGIC SW VDDIO PP VR5 Controller Vout range 4.9v-5.1v Vout 5V VR1 Controller Vout range 0.95v-1.05v Vout 1.00V VR3 Controller Vout range 3.23v-3.34v Vout 3.3V VDDIO PGVR2 DDRID DRVHVR4 V33ARTC VDDIO PGVR4 VSA VDDIO VDDIO TTL VDDPG PP VSB VSC VSD VSE ENA ENB ENC END ENE ENF ENG PGA PGB PGC PGD PGE PGF PGG POWER MONITOR VINVR2 [2X] SWVR2 [2X] PGNDVR2 [2X] FBVR2P FBVR2N VREGVR2 VSF VSG PPATH LOGIC TTL DCH REF VDDIO TTL ENLVA VDDIO TTL VDDLVS OD/PP LVA LVB ILIMVR5LS VREGVR1 SHUTDOWNZ STANDBYZ RESETZ VDDLV PGH ENH VSH SW VIN5VSW EN5VSW VREGVR4 ILIMVR3LS ILIMVR3HS VINVR3 VCOMP TRIPZ OEM VCOMP VDDIO PGVR3 NVDCZ OD/PP OD/PP TTL TTL VDDIO TTL OD/PP OD/PP OD/PP VDDIO OD/PP c TPS650830 V33A_DSW V100S V33A_DSW (EC_VCC) V3.3S COMP Comp_Mode Comp_PG_mod e Enable Logic Pgood_logic COMP COMP 1 - ENA & V33APCHCNT PGOOD A A COMP 1 0 ENB & V18U25UCNT ENB & V18U25UCNT B COMP - ENC PGOOD C C COMP 1 0 END & VCCIOCNT END & VCCIOCNT D COMP 1 0 ENE ENA & V33APCHCNT E COMP 1 0 ENF PGOOD F F COMP 1 - ENG PGOOD G G Volume #1 - Copyright © 2016, Texas Instruments Incorporated 138 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated 7.2.4 Specific Application - TPS650830 Powering the Intel SkyLake and Kabylake Platform Volume Configuration Volume configuration is the lowest cost and smallest solution for SkyLake and Kabylake power. It combines multiple same voltage rails into one rail reducing cost and size. Load switches are utilized to separate the rails and power the system with correct sequencing. The PMIC controls these load switches with the power good comparators. The TPS65083x also supports Premium configurations, see TPS650831 and TPS650832 or literature numbers: SLVSCS5 and SLVSCS6. Figure 7-12. TPS650830 Volume Application Diagram |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
