PIFE32251B-R68MS datasheet(139/157 Pages) TI1

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139

TPS650830

www.ti.com

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Application and Implementation

7.2.4.1

Design Requirements

The deisgn requirements are set by the Intel SkyLake and Kabylake Platform. Below are the requirements

of the power supply system. This procedure assumes the system is a 2S NVDC system but, the

TPS65083x supports 3S NVDC, as well as non-NVDC systems. 2S NVDC system has an input voltage

range of 5.4 V to 8.7 V.

•

There must be 9 separate voltage rails:

–

V5A_DS3 - 5 V, IMAX = 3.5 A

–

V3.3A_DSW - 3.3 V, IMAX = 3.5 A

–

V3.3A_PCH - 3.3 V, IMAX = 3 A

–

V1.00A - 1.0 V, IMAX = 4.9 A

–

VCCIO - 1.0 V, IMAX = 2.9 A

–

V1.8A - 1.8 V, IMAX = 1 A

–

V1.8U - 1.8 V, IMAX = 1 A

–

VDDQ - 1.2 V, IMAX = 7.5 A

–

VTT - 0.6 V, IMAX = ±1A

•

All rails must have maximum tolerance of ±5% of the nominal voltage at all times with load transients.

–

Load Transients are defined as 0% to 70%, 70% to 0%, 30% to 100% and 100% to 30% load

current steps relative of the IMAX current defined for each rail.

•

Maximum height of components = 1.8 mm.

•

Sequence in the order below:

–

V3.3A_DSW with VIN supplied

–

V1.8A with VIN supplied

–

V5A_DS3 with SLP_SUS# transition to HIGH

–

V3.3A_PCH with SLP_SUS# transition to HIGH

–

V1.00A with SLP_SUS# transition to HIGH

–

VDDQ with SLP_S4# transition to HIGH

–

V1.8U with SLP_S4# transition to HIGH

–

VCCIO with SLP_S3# transition to HIGH

–

VTT with DDR_VTT_CTRL / SLP_S0# transition to HIGH

7.2.4.2

Detailed Design Procedure

The TPS650830 supplies 6 voltage rails and controls 3 load switches to meet the sequence order for the

V3.3A_PCH, V1.8U, and VCCIO rails.

•

VR1 supplies the V1.00A rail and the VCCIO rail with a load switch.

•

VR2 supplies the V1.8A rail and the V1.8U rail with a load switch.

•

VR3 supplies the V3.3A_DSW rail and the V3.3A_PCH rail with a load switch.

•

VR4 supplies the VDDQ rail and the VINLDO1 for termination.

•

VR5 supplies the V5A_DS3 rail.

•

VLDO1 supplies the VTT rail.

To meet the sequencing requirement the power goods of the VRs and PG comparators are feed back into

the enables for the VRs and comparators. The 5 external control signals SLP_SUS#, _S4#, _S3#, _S0#,

and DDR_VTT_CTRL are responsible for transitioning the system from sleep state to sleep state and the

reverse sequencing.

Since, the requirements are for a 2S NVDC system the NVDCZ pin should be tied LOW.

PIFE32251B-R68MS 데이터시트(PDF) 139 Page - Texas Instruments

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