PIFE32251B-R68MS datasheet(144/157 Pages) TI1

144 / 157 page

10 mil

6 mil

4 mil

Inner Balls

= Ball Pad

= Via, with 10 mil pad

and 6 mil drill

= Top Layer Trace

= Inner 1 / Bottom

Layer Trace

= Inner 2 / Bottom

Layer Trace

144

TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Layout

9.1

Layout Guidelines

For all switching power supplies, the layout is an important step in the design, especially at high peak

currents and high switching frequencies. If the layout is not carefully done, the regulator could show

stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path

and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed

as close as possible to the IC. Use a common ground node for power ground and a different one for

control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to

one of the ground pins of the IC.

There are 2 packages available for the TPS65083x, the ZAJ and ZCG. The ZAJ is a 7-mm x 7-mm BGA

with 0.5-mm ball pitch. The ZCG is a 9-mm x 9-mm BGA with 0.5-mm ball pitch but, some of the inner

balls have been removed for easier routing. Both packages preform relatively the same and the decision

between which package is best for the application depends on the space constraints and routing

technology used.

9.1.1

Fanout for ZAJ using Type 4 Routing

This small 7-mm x 7-mm package utilizes the Type 4 routing technique to decrease system board area as

much as possible. This Type 4 routing has vias in pad, blind and buried vias, and minimum trace width /

spacing of 4 mils.

Figure 9-1. Fanout for ZAJ Package Using Type 4 Routing

PIFE32251B-R68MS 데이터시트(PDF) 144 Page - Texas Instruments