DSP56364 datasheet(22/148 Pages) FREESCALE

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Phase Lock Loop (PLL) Characteristics

DSP56364 Technical Data, Rev. 4.1

3-6

Freescale Semiconductor

3.8

Phase Lock Loop (PLL) Characteristics

Table 3-5 Clock Operation

No.

Characteristics

Symbol

Min

Max

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns maximum.

100.0

EXTAL input high1, 2

• With PLL disabled (46.7%–53.3% duty cycle6)

1 Measured at 50% of the input transition.

2 The maximum value for PLL enabled is given for minimum VCO and maximum MF.

ETH

4.67 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle6)

4.25 ns

157.0

μs

EXTAL input low1, 2

• With PLL disabled (46.7%–53.3% duty cycle6)ETL

4.67 ns

∞

• With PLL enabled (42.5%–57.5% duty cycle6)

4.25 ns

157.0

μs

EXTAL cycle time2

• With PLL disabled

ETC

10.00 ns

∞

• With PLL enabled

10.00 ns

273.1

μs

Table 3-6 PLL Characteristics

Characteristics

Min

Max

Unit

VCO frequency when PLL enabled (MF × Ef × 2/PDF)

200

MHz

PLL external capacitor (PCAP pin to VCCP) (CPCAP

1 C

PCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for

CPCAP can be computed from one of the following equations:

(MF x 680)-120, for MF

≤ 4, or

MF x 1100, for MF > 4.

•@ MF

≤ 4(MF × 580) − 100

(MF

× 780) − 140

• @ MF > 4

× 830

× 1470

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