DSP56364 datasheet(35/148 Pages) FREESCALE

35 / 148 page

External Memory Expansion Port (Port A)

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-19

152

Last RD assertion to RAS deassertion

tROH

1.5

× T

C − 4.0

71.0

—

46.0

—

153

RD assertion to data valid

tGA

TC − 7.5

—

42.5

—

25.8

154

RD deassertion to data not valid 6

tGZ

0.0

—

0.0

—

155

WR assertion to data active

0.75

× T

C − 0.3

37.2

—

24.7

—

156

WR deassertion to data high

impedance

0.25

× T

—

12.5

—

8.3

1 The number of wait states for Page mode access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t

PC equals 2 × TC for

read-after-read or write-after-write sequences).

4 Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See

Figure 3-14.).

5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access.

6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued)

No.

Characteristics

Symbol

Expression

20 MHz4

30 MHz4

Unit

Min

Max

Min

Max

DSP56364 데이터시트(PDF) 35 Page - Freescale Semiconductor, Inc

DSP56364 데이터시트(HTML) 35 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL