DSP56364 datasheet(63/148 Pages) FREESCALE

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Enhanced Serial Audio Interface Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-47

3.13

Enhanced Serial Audio Interface Timing

Table 3-20 Enhanced Serial Audio Interface Timing

No.

Characteristics1, 2, 3

Symbol

Expression

Min

Max

Condition4 Unit

430

Clock cycle5

tSSICC

× T

40.0

—

i ck

× T

30.0

—

x ck

TXC:max[3*tc; t454]

40.0

—

x ck

431

Clock high period

• For internal clock

—

× T

C − 10.0

10.0

—

• For external clock

1.5

× T

15.0

—

432

Clock low period

• For internal clock

—

× TC − 10.0

10.0

—

• For external clock

1.5

× T

15.0

—

433

RXC rising edge to FSR out (bl) high

—

37.0

22.0

x ck

i ck a

434

RXC rising edge to FSR out (bl) low

—

37.0

22.0

x ck

i ck a

435

RXC rising edge to FSR out (wr) high6

——

—

39.0

24.0

x ck

i ck a

436

RXC rising edge to FSR out (wr) low6

——

—

39.0

24.0

x ck

i ck a

437

RXC rising edge to FSR out (wl) high

—

36.0

21.0

x ck

i ck a

438

RXC rising edge to FSR out (wl) low

—

37.0

22.0

x ck

i ck a

439

Data in setup time before RXC (SCK in

synchronous mode) falling edge

——

0.0

19.0

—

x ck

i ck

440

Data in hold time after RXC falling edge

—

5.0

3.0

—

x ck

i ck

441

FSR input (bl, wr) high before RXC falling

edge6

——

23.0

1.0

—

x ck

i ck a

442

FSR input (wl) high before RXC falling edge

—

1.0

23.0

—

x ck

i ck a

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