DSP56364 datasheet(29/148 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-13

101

Address and AA valid to WR assertion

tAS

0.25

× T

C − 2.0

[WS = 1]

0.5

—

0.75

× T

C − 2.0

≤ WS ≤ 3]

5.5

—

1.25

× T

C − 2.0

[WS

≥ 4]

10.5

—

102

WR assertion pulse width

tWP

1.5

× T

C − 4.0

[WS = 1]

11.0

—

All frequencies:

× T

C − 4.0

≤ WS ≤ 3]

16.0

—

(WS

− 0.5) × T

C − 4.0

[WS

≥ 4]

31.0

—

103

WR deassertion to address not valid

tWR

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.5

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

10.5

—

2.25

× T

C − 2.0

[WS

≥ 8]

20.5

—

All frequencies:

1.25

× T

C − 4.0

≤ WS ≤ 7]

8.5

—

2.25

× T

C − 4.0

[WS

≥ 8]

18.5

—

104

Address and AA valid to input data valid

tAA, tAC

(WS + 0.75)

× T

C − 7.0

[WS

≥ 1]

—10.5

105

RD assertion to input data valid

tOE

(WS + 0.25)

× T

C − 7.0

[WS

≥ 1]

—5.5

106

RD deassertion to data not valid (data hold time)

tOHZ

0.0

—

107

Address valid to WR deassertion3

tAW

(WS + 0.75)

× T

C − 4.0

[WS

≥ 1]

13.5

—

Table 3-8 SRAM Read and Write Accesses1 (continued)

No.

Characteristics

Symbol

Expression2

Min

Max

Unit

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