DSP56364 datasheet(50/148 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56364 Technical Data, Rev. 4.1

3-34

Freescale Semiconductor

173

Column address valid to CAS assertion

tASC

0.75

× T

C − 4.0

3.5

—

174

CAS assertion to column address not valid

tCAH

6.25

× T

C − 4.0

58.5

—

175

RAS assertion to column address not valid

tAR

9.75

× T

C − 4.0

93.5

—

176

Column address valid to RAS deassertion

tRAL

× T

C − 4.0

66.0

—

177

WR deassertion to CAS assertion

tRCS

× T

C − 3.8

46.2

—

178

CAS deassertion to WR4 assertion

tRCH

1.75

× T

C − 3.7

13.8

—

179

RAS deassertion to WR4 assertion

tRRH

0.25

× T

C − 2.0

0.5

—

180

CAS assertion to WR deassertion

tWCH

× T

C − 4.2

55.8

—

181

RAS assertion to WR deassertion

tWCR

9.5

× T

C − 4.2

90.8

—

182

WR assertion pulse width

tWP

15.5

× T

C − 4.5

150.5

—

183

WR assertion to RAS deassertion

tRWL

15.75

× T

C − 4.3

153.2

—

184

WR assertion to CAS deassertion

tCWL

14.25

× T

C − 4.3

138.2

—

185

Data valid to CAS assertion (write)

tDS

8.75

× T

C − 4.0

83.5

—

186

CAS assertion to data not valid (write)

tDH

6.25

× T

C − 4.0

58.5

—

187

RAS assertion to data not valid (write)

tDHR

9.75

× T

C − 4.0

93.5

—

188

WR assertion to CAS assertion

tWCS

9.5

× T

C − 4.3

90.7

—

189

CAS assertion to RAS assertion (refresh)

tCSR

1.5

× T

C − 4.0

11.0

—

190

RAS deassertion to CAS assertion (refresh)

tRPC

4.75

× T

C − 4.0

43.5

—

191

RD assertion to RAS deassertion

tROH

15.5

× T

C − 4.0

151.0

—

192

RD assertion to data valid

tGA

× T

C − 5.7

—

134.3

193

RD deassertion to data not valid3

tGZ

0.0

—

194

WR assertion to data active

0.75

× T

C − 0.3

7.2

—

195

WR deassertion to data high impedance

0.25

× T

—2.5

1 The number of wait states for out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

4 Either t

RCH or tRRH must be satisfied for read cycles.

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)

No.

Characteristics3

Symbol

Expression

Min

Max

Unit

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