DSP56364 datasheet(62/148 Pages) FREESCALE

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Serial Host Interface (SHI) I2C Protocol Timing

DSP56364 Technical Data, Rev. 4.1

3-46

Freescale Semiconductor

In I2C mode, the user may select a value for the programmed serial clock cycle from

The programmed serial clock cycle (TI2CCP), SCL rise time (TR), and the filters selected should be chosen

in order to achieve the desired SCL frequency, as shown in Table 3-19.

EXAMPLE:

For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment

(FSCL = 100 KHz (i.e. TSCL = 10μs), TR = 1000ns), with filters bypassed

Choosing HRS = 0 gives

Thus the HDM[7:0] value should be programmed to $38 (=56).

Figure 3-22 I2C Timing

Table 3-19 SCL Serial Clock Cycle Generated as Master

Filters bypassed

TI2CCP + 2.5 × TC + 45ns + TR

Narrow filters enabled

TI2CCP + 2.5 × TC + 135ns + TR

Wide filters enabled

TI2CCP + 2.5 × TC + 223ns + TR

6TC if HDMS 50

[]

and HRS

()

4096 TC if HDMS 70

[]

and HRS

()

2CCP

μs 2.5 10ns 45ns

–

1000ns

–

893ns

HDM 7 0

[]

8930ns

() 210ns

() 1

–

⁄

55.8

Start

SCL

HREQ

SDA

ACK

MSB

LSB

Stop

171

Stop

173

176

175

177

178

180

179

172

186

182

183

189

174

188

184

187

AA0275

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