DSP56364 datasheet(30/148 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56364 Technical Data, Rev. 4.1

3-14

Freescale Semiconductor

108

Data valid to WR deassertion (data setup time)

tDS (tDW)(WS − 0.25) × TC − 3.0

[WS

≥ 1]

4.5

—

109

Data hold time from WR deassertion

tDH

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.5

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

10.5

—

2.25

× T

C − 2.0

[WS

≥ 8]

20.5

—

113

RD deassertion time

0.75

× T

C − 4.0

≤ WS ≤ 3]

3.5

—

1.75

× T

C − 4.0

≤ WS ≤ 7]

13.5

—

2.75

× T

C − 4.0

[WS

≥ 8]

23.5

—

114

WR deassertion time

0.5

× T

C − 4.0

[WS = 1]

1.0

—

TC − 2.0

≤ WS ≤ 3]

6.0

—

2.5

× T

C − 4.0

≤ WS ≤ 7]

21.0

—

3.5

× T

C − 4.0

[WS

≥ 8]

31.0

—

115

Address valid to RD assertion

0.5

× T

C − 4.0

1.0

—

116

RD assertion pulse width

(WS + 0.25)

× T

C −4.0

8.5

—

117

RD deassertion to address not valid

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.5

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

10.5

—

2.25

× T

C − 2.0

[WS

≥ 8]

20.5

—

Table 3-8 SRAM Read and Write Accesses1 (continued)

No.

Characteristics

Symbol

Expression2

Min

Max

Unit

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