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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56364 데이터시트(PDF) 31 Page - Freescale Semiconductor, Inc |
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DSP56364 데이터시트(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 148 page  External Memory Expansion Port (Port A) DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor 3-15 Figure 3-9 SRAM Read Access 118 TA setup before RD or WR deassertion4 0.25 × T C + 2.0 4.5 — ns 119 TA hold after RD or WR deassertion 0 — ns 1 All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc 2 WS is the number of wait states specified in the BCR. 3 Timings 100, 107 are guaranteed by design, not tested. 4 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active. Table 3-8 SRAM Read and Write Accesses1 (continued) No. Characteristics Symbol Expression2 Min Max Unit A0–A17 RD WR D0–D7 AA0–AA1 115 105 106 113 104 116 117 100 AA0468 TA 119 Data In 118 |
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