DSP56364 datasheet(23/148 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-7

3.9

Reset, Stop, Mode Select, and Interrupt Timing

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1

No.

Characteristics

Expression2

Min

Max

Unit

8Delay from

RESET assertion to all pins at reset value3

——

26.0

Required

RESET duration4

• Power on, external clock generator, PLL disabled

× ET

500.0

—

• Power on, external clock generator, PLL enabled

1000

× ET

10.0

—

• Power on, internal oscillator

75000

× ET

0.75

—

μs

• During STOP, XTAL disabled (PCTL Bit 16 = 0)

75000

× ET

0.75

—

• During STOP, XTAL enabled (PCTL Bit 16 = 1)

2.5

× T

25.0

—

• During normal operation

2.5

× T

25.0

—

Delay from asynchronous

RESET deassertion to first

external address output (internal reset deassertion)5

• Minimum

3.25

× T

C + 2.0

34.5

—

• Maximum

20.25 TC + 7.50

—

211.5

Mode select setup time

30.0

—

Mode select hold time

0.0

—

Minimum edge-triggered interrupt request assertion width

6.6

—

Minimum edge-triggered interrupt request deassertion width

6.6

—

Delay from

IRQA, IRQB, IRQD, NMI assertion to external

memory access address out valid

• Caused by first interrupt instruction fetch

4.25

× T

C + 2.0

44.5

—

• Caused by first interrupt instruction execution

7.25

× T

C + 2.0

74.5

—

Delay from

IRQA, IRQB, IRQD, NMI assertion to

general-purpose transfer output valid caused by first

interrupt instruction execution

× T

C + 5.0

105.0

—

Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for level

sensitive fast interrupts 6, 7

3.75

× T

C + WS × TC – 10.94

—

Delay from

RD assertion to interrupt request deassertion

for level sensitive fast interrupts6, 7

3.25

× T

C + WS × TC – 10.94

—

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