DSP56364 datasheet(61/148 Pages) FREESCALE

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Serial Host Interface (SHI) I2C Protocol Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-45

3.12.1

Programming the Serial Clock

The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[5:0] and HRS bits of the

HCKR (SHI clock control register).

The expression for TI2CCP is

where

HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is

operational. When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits.

A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.

186 First SCL sampling edge to HREQ output

deassertion

TNG;RQO

• Filters bypassed

× T

C + 30

—

• Narrow filters enabled

× T

C + 120

—

140

—

140

• Wide filters enabled

× T

C + 208

—

228

—

228

187 Last SCL edge to HREQ output not

deasserted

TAS;RQO

• Filters bypassed

× T

C + 30

—

• Narrow filters enabled

× T

C + 80

100

—

100

—

• Wide filters enabled

× T

C + 135

155

—

155

—

188 HREQ in assertion to first SCL edge

TAS;RQI

0.5

× T

I2CCP -

0.5

× T

C - 21

• Filters bypassed

4327

—

927

—

• Narrow filters enabled

4282

—

882

—

• Wide filters enabled

4238

—

838

—

1 R

P (min) = 1.5 k¾

Table 3-18 SHI I2C Protocol Timing (continued)

Standard I2C1

No.

Characteristics

Symbol/

Expression

Standard-Mode

Fast-Mode

Unit

Min

Max

Min

Max

2CCP

TC 2

HDM 7 0

[] 1

()

(

1HRS

–

()

)

[]

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