| 전자부품 데이터시트 검색엔진 |
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DSP56364 데이터시트(PDF) 24 Page - Freescale Semiconductor, Inc |
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DSP56364 데이터시트(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 148 page ![]() Reset, Stop, Mode Select, and Interrupt Timing DSP56364 Technical Data, Rev. 4.1 3-8 Freescale Semiconductor 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts6, 7 ns • DRAM for all WS (WS + 3.5) × T C – 10.94 — — • SRAM WS = 1 (WS + 3.5) × T C – 10.94 — — • SRAM WS = 2, 3 (WS + 3) × T C – 10.94 — — •SRAM WS ≥ 4 (WS + 2.5) × T C – 10.94 — — 24 Duration for IRQA assertion to recover from Stop state 5.9 — 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)3, 8 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLC × ET C × PDF + (128 K − PLC/2) × T C 1.3 13.6 ms • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLC × ET C × PDF + (23.75 ± 0.5) × T C 232.5 ns 12.3 ms • PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) (8.25 ± 0.5) × T C 77.5 87.5 ns 26 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)3, 8 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLC × ET C × PDF + (128 K − PLC/2) × T C 13.6 — ms • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLC × ET C × PDF + (20.5 ± 0.5) × T C 12.3 — ms • PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) 5.5 × T C 55.0 — ns 27 Interrupt Requests Rate • ESAI, SCI 12TC — 120.0 ns •DMA 8TC —80.0 ns • IRQ, NMI (edge trigger) 8TC —80.0 ns • IRQ, NMI (level trigger) 12TC — 120.0 ns 28 DMA Requests Rate • Data read from ESAI, SCI 6TC —60.0 ns • Data write to ESAI, SCI 7TC —70.0 ns • IRQ, NMI (edge trigger) 3TC —30.0 ns Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued) No. Characteristics Expression2 Min Max Unit |
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