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DSP56364 데이터시트(PDF) 40 Page - Freescale Semiconductor, Inc

부품명 DSP56364
상세설명  24-Bit Audio Digital Signal Processor
PDF  148 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56364 데이터시트(HTML) 40 Page - Freescale Semiconductor, Inc

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External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4.1
3-24
Freescale Semiconductor
140
Column address valid to CAS assertion
tASC
TC − 4.0
6.0
ns
141
CAS assertion to column address not valid
tCAH
3.5
× T
C − 4.0
31.0
ns
142
Last column address valid to RAS deassertion
tRAL
5
× T
C − 4.0
46.0
ns
143
WR deassertion to CAS assertion
tRCS
1.25
× T
C − 4.0
8.5
ns
144
CAS deassertion to WR assertion
tRCH
1.25
× T
C − 4.0
8.5
ns
145
CAS assertion to WR deassertion
tWCH
3.25
× T
C − 4.2
28.3
ns
146
WR assertion pulse width
tWP
4.5
× T
C − 4.5
40.5
ns
147
Last WR assertion to RAS deassertion
tRWL
4.75
× T
C − 4.3
43.2
ns
148
WR assertion to CAS deassertion
tCWL
3.75
× T
C − 4.3
33.2
ns
149
Data valid to CAS assertion (write)
tDS
0.5
× T
C − 4.0
1.0
ns
150
CAS assertion to data not valid (write)
tDH
3.5
× T
C − 4.0
31.0
ns
151
WR assertion to CAS assertion
tWCS
1.25
× T
C − 4.3
8.2
ns
152
Last RD assertion to RAS deassertion
tROH
4.5
× T
C − 4.0
41.0
ns
153
RD assertion to data valid
tGA
3.25
× T
C − 7.0
25.5
ns
154
RD deassertion to data not valid6
tGZ
0.0
ns
155
WR assertion to data active
0.75
× T
C − 0.3
7.2
ns
156
WR deassertion to data high impedance
0.25
× T
C
—2.5
ns
1 The number of wait states for Page mode access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 The asynchronous delays specified in the expressions are valid for DSP56364.
4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
PC equals 3 × TC for
read-after-read or write-after-write sequences).
5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF and not tGZ.
Table 3-12 DRAM Page Mode Timings, Four Wait States1, 2, 3 (continued)
No.
Characteristics
Symbol
Expression4
Min
Max
Unit



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