DSP56364 datasheet(54/148 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56364 Technical Data, Rev. 4.1

3-38

Freescale Semiconductor

143

Serial clock low period

Master

Bypassed

0.5

×t

SPICC –10

—

Narrow

0.5

×t

SPICC –10

—

Wide

0.5

×t

SPICC –10

131

—

Slave

Bypassed

2.5

×T

C+12

—

Narrow

2.5

×T

C+102

127

—

Wide

2.5

×T

C+189

214

—

144

Serial clock rise/fall time

Master

—

Slave

—

2000

146

SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

3.5

×T

C+15

—

Narrow

—

Wide

—

CPHA = 1

Slave

Bypassed

—

Narrow

—

Wide

—

147

Last SCK edge to SS not asserted

Slave

Bypassed

—

Narrow

102

—

Wide

189

—

148

Data input valid to SCK edge (data input set-up

time)

Master/

Slave

Bypassed

—

Narrow

MAX{(20-TC), 0}

—

Wide

MAX{(40-TC), 0}

—

149

SCK last sampling edge to data input not valid

Master/

Slave

Bypassed

2.5

×T

C+10

—

Narrow

2.5

×T

C+30

—

Wide

2.5

×T

C+50

—

150

SS assertion to data out active

Slave

—

151

SS deassertion to data high impedance

Slave

—

Table 3-17 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics

Mode

Filter

Mode

Expression

Min

Max

Unit

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