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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56364 데이터시트(PDF) 48 Page - Freescale Semiconductor, Inc |
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DSP56364 데이터시트(HTML) 48 Page - Freescale Semiconductor, Inc |
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48 / 148 page  External Memory Expansion Port (Port A) DSP56364 Technical Data, Rev. 4.1 3-32 Freescale Semiconductor 164 CAS assertion to RAS deassertion tRSH 5.25 × T C − 4.0 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × T C − 4.0 58.5 — ns 166 CAS assertion pulse width tCAS 3.75 × T C − 4.0 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × T C ± 4.0 21.0 29.0 ns 168 RAS assertion to column address valid tRAD 1.75 × T C ± 4.0 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × T C − 4.0 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × T C − 4.0 38.5 — ns 171 Row address valid to RAS assertion tASR 4.25 × T C − 4.0 38.5 — ns 172 RAS assertion to row address not valid tRAH 1.75 × T C − 4.0 13.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × T C − 4.0 3.5 — ns 174 CAS assertion to column address not valid tCAH 5.25 × T C − 4.0 48.5 — ns 175 RAS assertion to column address not valid tAR 7.75 × T C − 4.0 73.5 — ns 176 Column address valid to RAS deassertion tRAL 6 × T C − 4.0 56.0 — ns 177 WR deassertion to CAS assertion tRCS 3.0 × T C − 4.0 26.0 — ns 178 CAS deassertion to WR5 assertion tRCH 1.75 × T C − 4.0 13.5 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × T C − 2.0 0.5 — ns 180 CAS assertion to WR deassertion tWCH 5 × T C − 4.2 45.8 — ns 181 RAS assertion to WR deassertion tWCR 7.5 × T C − 4.2 70.8 — ns 182 WR assertion pulse width tWP 11.5 × T C − 4.5 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × T C − 4.3 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × T C − 4.3 103.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × T C − 4.0 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × T C − 4.0 48.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.75 × T C − 4.0 73.5 — ns 188 WR assertion to CAS assertion tWCS 6.5 × T C − 4.3 60.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × T C − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 2.75 × T C − 4.0 23.5 — ns Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued) No. Characteristics3 Symbol Expression4 Min Max Unit |
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