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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56364 데이터시트(PDF) 53 Page - Freescale Semiconductor, Inc |
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DSP56364 데이터시트(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 148 page  Serial Host Interface SPI Protocol Timing DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor 3-37 Figure 3-17 DRAM Refresh Access 3.11 Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing No. Characteristics Mode Filter Mode Expression Min Max Unit 140 Tolerable spike width on clock or data in — Bypassed — — 0 ns Narrow — — 50 ns Wide — — 100 ns 141 Minimum serial clock cycle = tSPICC(min) Master Bypassed 6 ×T C+46 106 — ns Narrow 6 ×T C+152 212 — ns Wide 6 ×T C+223 283 — ns 142 Serial clock high period Master Bypassed 0.5 ×t SPICC –10 43 — ns Narrow 0.5 ×t SPICC –10 96 — ns Wide 0.5 ×t SPICC –10 131 — ns Slave Bypassed 2.5 ×T C+12 37 — ns Narrow 2.5 ×T C+102 127 — ns Wide 2.5 ×T C+189 214 — ns RAS CAS WR 157 163 162 162 190 170 165 189 177 AA0478 |
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