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DSP56364 데이터시트(PDF) 47 Page - Freescale Semiconductor, Inc

부품명 DSP56364
상세설명  24-Bit Audio Digital Signal Processor
PDF  148 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56364 데이터시트(HTML) 47 Page - Freescale Semiconductor, Inc

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External Memory Expansion Port (Port A)
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
3-31
186
CAS assertion to data not valid (write)
tDH
3.25
× T
C − 4.0
45.2
36.6
ns
187
RAS assertion to data not valid (write)
tDHR
5.75
× T
C − 4.0
83.1
67.9
ns
188
WR assertion to CAS assertion
tWCS
5.5
× T
C − 4.3
79.0
64.5
ns
189
CAS assertion to RAS assertion
(refresh)
tCSR
1.5
× T
C − 4.0
18.7
14.8
ns
190
RAS deassertion to CAS assertion
(refresh)
tRPC
1.75
× T
C − 4.0
22.5
17.9
ns
191
RD assertion to RAS deassertion
tROH
8.5
× T
C − 4.0
124.8
102.3
ns
192
RD assertion to data valid
tGA
7.5
× T
C − 7.5
106.1
ns
7.5
× T
C − 6.5
87.3
ns
193
RD deassertion to data not valid3
tGZ
0.0
0.0
0.0
ns
194
WR assertion to data active
0.75
× T
C − 0.3
11.1
9.1
ns
195
WR deassertion to data high
impedance
0.25
× T
C
—3.8
—3.1
ns
1 The number of wait states for out-of-page access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF and not tGZ.
4 The asynchronous delays specified in the expressions are valid for DSP56364.
5 Either t
RCH or tRRH must be satisfied for read cycles.
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
No.
Characteristics3
Symbol
Expression4
Min
Max
Unit
157
Random read or write cycle time
tRC
12
× T
C
120.0
ns
158
RAS assertion to data valid (read)
tRAC
6.25
× T
C − 7.0
55.5
ns
159
CAS assertion to data valid (read)
tCAC
3.75
× T
C − 7.0
30.5
ns
160
Column address valid to data valid (read)
tAA
4.5
× T
C − 7.0
38.0
ns
161
CAS deassertion to data not valid (read hold time)
tOFF
0.0
ns
162
RAS deassertion to RAS assertion
tRP
4.25
× T
C − 4.0
38.5
ns
163
RAS assertion pulse width
tRAS
7.75
× T
C − 4.0
73.5
ns
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued)
No.
Characteristics3
Symbol
Expression4
66 MHz
80 MHz
Unit
Min
Max
Min
Max



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