DSP56364 datasheet(55/148 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56364 Technical Data, Rev. 4.1

Freescale Semiconductor

3-39

152

SCK edge to data out valid

(data out delay time)

Master/

Slave

Bypassed

×T

C+33

—

Narrow

×T

C+123

—

143

Wide

×T

C+210

—

230

153

SCK edge to data out not valid

(data out hold time)

Master/

Slave

Bypassed

TC+5

—

Narrow

TC+55

—

Wide

TC+106

116

—

154

SS assertion to data out valid

(CPHA = 0)

Slave

—

TC+33

—

157

First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

2.5

×T

C+30

—

Narrow

2.5

×T

C+120

—

145

Wide

2.5

×T

C+217

—

242

158

Last SCK sampling edge to HREQ output not

deasserted (CPHA = 1)

Slave

Bypassed

2.5

×T

C+30

—

Narrow

2.5

×T

C+80

105

—

Wide

2.5

×T

C+136

161

—

159

SS deassertion to HREQ output not deasserted

(CPHA = 0)

Slave

—

2.5

×T

C+30

—

160

SS deassertion pulse width (CPHA = 0)

Slave

—

TC+6

—

161

HREQ in assertion to first SCK edge

Master

Bypassed

0.5

× t

SPICC +

2.5

×T

C+43

121

—

Narrow

0.5

×t

SPICC +

2.5

×T

C+43

174

—

Wide

0.5

×t

SPICC +

2.5

×T

C+43

209

—

162

HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

163

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

Note: Periodically sampled, not 100% tested

Table 3-17 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics

Mode

Filter

Mode

Expression

Min

Max

Unit

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