ADSP-SC596 datasheet(3/134 Pages) AD

3 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 3 of 134

May 2022

GENERAL DESCRIPTION

The ADSP-SC595/SC596/SC598 processors are members of the

SHARC

® family of products. The processors are based on the

SHARC+® dual-core and the Arm® Cortex®-A55 core. The

ADSP-SC595/SC596/SC598 SHARC processors are members of

the single-instruction, multiple data (SIMD) SHARC family of

digital signal processors (DSPs) that feature Analog Devices

Super Harvard Architecture. These 32-bit/40-bit/64-bit float-

ing-point processors are optimized for high performance

audio/floating-point applications with large on-chip static ran-

dom-access memory (SRAM), multiple internal buses that

eliminate input/output (I/O) bottlenecks, and innovative digital

audio interfaces (DAI). New additions to the SHARC+ core

include cache enhancements and branch prediction, while

maintaining instruction set compatibility to previous SHARC

products.

By integrating a set of industry leading system peripherals and

memory, the Arm Cortex-A55 and SHARC processor is the

platform of choice for applications that require programmabil-

ity similar to reduced instruction set computing (RISC),

multimedia support, and leading edge signal processing in one

integrated package. These applications span a wide array of

markets, including automotive, professional audio, and indus-

trial-based applications that require high floating-point

performance.

Table 1 provides comparison information for features that vary

across the standard processors.

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