ADSP-SC596 datasheet(74/134 Pages) AD

74 / 134 page

Rev. PrD

Page 74 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

LPs DDR Mode

Link ports DDR mode is a same edge protocol. It drives and samples data on the same edge of the clock. Positive-edge-driven data from

Tx is sampled on the same positive edge by Rx, and negative-edge-driven data from Tx is sampled on the same negative edge by Rx.

Table 41. LPs DDR—Receive1

1 Specifications apply to LP0 and LP1.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

fLCLKREXT

LPx_CLK Frequency

125

MHz

tSLDCL

Data Setup Before LPx_CLK

0.85

tHLDCL

Data Hold After LPx_CLK

1.45

tLCLKEW

LPx_CLK Period2

2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external

LPx_CLK ideal maximum frequency, see the fLCLKRTEXT specification in Table 22.

tLCLKREXT – 1

tLCLKRWL

LPx_CLK Width Low2

0.5 × tLCLKREXT

tLCLKRWH

LPx_CLK Width High2

0.5 × tLCLKREXT

Switching Characteristic

tDLALC

LPx_ACK Low Delay After LPx_CLK Low3

3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.

1.5 × tCDU_CLKO8 + 4

2.5 × tCDU_CLKO8 + 12

Figure 12. LPs DDR—Receive

tSLDCL

tLCLKRWH

tLCLKRWL

tLCLKEW

tDLALC

LPx_CLK

LPx_D3–0

LPx_ACK (OUT)

tHLDCL

tSLDCL

tHLDCL

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