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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADSP-SC596 데이터시트(PDF) 61 Page - Analog Devices |
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ADSP-SC596 데이터시트(HTML) 61 Page - Analog Devices |
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61 / 134 page  Rev. PrD | Page 61 of 134 | May 2022 ADSP-SC595/SC596/SC598 Preliminary Technical Data Preliminary Clock Related Operating Conditions Table 22 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all speed grades except where noted. Table 22. Preliminary Clock Operating Conditions Parameter Conditions Min Typ Max Unit fCCLK SHARC+ Core Clock (CCLK) Frequency fCCLK = 2 × fSYSCLK 600 1000 MHz fARMCCLK Arm Cortex-A55 Core Clock (CCLK) Frequency fARMCCLK = 2 × fSYSCLK or fARMCCLK = fVCOCLK/3 600 1200 MHz fSYSCLK SYSCLK Frequency1 300 500 MHz fSCLK0 SCLK0 Frequency fSYSCLK = N × fSCLK0 where N = 2 or 4 or 6 30 125 MHz fSCLK1 SCLK1 Frequency fSYSCLK ≥ fSCLK1 333.33 MHz fDCLK DDR3 Clock (DCLK) Frequency2 All combinations are supported except for: [fCCLK > 800 MHz and Tj < 0°C and fCCLK:fDCLK = 2:1] 300 TBD MHz fOCLK Output Clock (OCLK) Frequency3 125 MHz fSYS_CLKOUTJ SYS_CLKOUT Period Jitter4, 5 ±2 % fLCLKTPROG Programmed Link Port Transmit Clock 125 MHz fLCLKREXT External Link Port Receive Clock6, 7 fLCLKREXT ≤ fOCLK_0 125 MHz fPCLKPROG Programmed PPI Clock When Transmitting Data and Frame Sync 62.5 MHz fPCLKPROG Programmed PPI Clock When Receiving Data or Frame Sync 50 MHz fPCLKEXT External PPI Clock When Receiving Data and Frame Sync6, 7 62.5 MHz fPCLKEXT External PPI Clock Transmitting Data or Frame Sync6, 7 50 MHz fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync 62.5 MHz fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync 31.25 MHz fSPTCLKEXT External SPT Clock When Receiving Data and Frame Sync6, 7 fSPTCLKEXT ≤ fSCLK0 62.5 MHz fSPTCLKEXT External SPT Clock Transmitting Data or Frame Sync6, 7 fSPTCLKEXT ≤ fSCLK0 31.25 MHz fSPICLKPROG Programmed SPI Clock When Transmitting Data fSPICLK:fSCLK0 ratio = 1:1 75 MHz fSPICLKPROG Programmed SPI Clock When Receiving Data fSPICLK:fSCLK0 ratio = 1:1 75 MHz fSPICLKPROG Programmed SPI Clock When Transmitting Data fSPICLK:fSCLK0 ratio = 1:2 62.5 MHz fSPICLKPROG Programmed SPI Clock When Receiving Data fSPICLK:fSCLK0 ratio = 1:2 62.5 MHz fSPICLKEXT External SPI Clock When Receiving Data6, 7 fSPICLKEXT ≤ fCDU_CLKO0 62.5 MHz fSPICLKEXT External SPI Clock When Transmitting Data6, 7 fSPICLKEXT ≤ fCDU_CLKO0 45 MHz fOSPICLKPROG Programmed OSPI Clock Without Data Training 62.5 MHz fOSPICLKPROG Programmed OSPI Clock With Data Training and Without DQS 80 MHz fOSPICLKPROG Programmed OSPI Clock Without Data Training and With DQS 125 MHz |
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