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ADSP-SC596 데이터시트(PDF) 77 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 77 Page - Analog Devices

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Rev. PrD
|
Page 77 of 134
|
May 2022
ADSP-SC595/SC596/SC598
Preliminary Technical Data
Table 44. SPORTs—Internal Clock1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
Frame Sync Setup Before SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
11
ns
tHFSI
Frame Sync Hold After SPTx_CLK
(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2
–0.5
ns
tSDRI
Receive Data Setup Before SPTx_CLK2
3.4
ns
tHDRI
Receive Data Hold After SPTx_CLK2
3.6
ns
Switching Characteristics
tDFSI
Frame Sync Delay After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
3.5
ns
tHOFSI
Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
–3
ns
tDDTI
Transmit Data Delay After SPTx_CLK3
3.5
ns
tHDTI
Transmit Data Hold After SPTx_CLK3
–3
ns
tSPTCLKIW
SPTx_CLK Width4
0.5 × tSPTCLKPROG – 1.5
ns
tSPTCLKW
SPTx_CLK Period4
tSPTCLKPROG – 1.5
ns
1 Specifications apply to all four SPORTs.
2 Referenced to the sample edge.
3 Referenced to drive edge.
4 See Table 22 for details on the minimum period that can be programmed for fSPTCLKPROG.



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