ADSP-SC596 datasheet(6/134 Pages) AD

6 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 6 of 134

May 2022

accesses are most efficient when one block stores data using the

DM bus for transfers, and the other block stores instructions

and data using the PM bus for transfers.

Using the DM and PM buses, with each bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The system configuration is flexible, but a typical configuration

is 512 kb DM, 128 kb PM, and 128 kb of instruction cache, with

the remaining L1 memory configured as SRAM. Each address-

able memory space outside the L1 memory can be accessed

either directly or via cache.

The memory map in Table 2 gives the L1 memory address space

and shows multiple L1 memory blocks offering a configurable

mix of SRAM and cache.

L1 Requester and Completer Ports

Each SHARC+ core has two requester/completer ports to and

from the system fabric. One requester port fetches instructions.

The second requester port drives data to the system world.

Completer Port 1 together with Completer Port 2 memory

direct memory access (MDMA) run conflict free access to the

individual memory blocks. For the completer port address, refer

to the L1 memory address map in Table 2.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks, assuming no

block conflicts. The total bandwidth is realized using both the

DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit

SYSCLK speed).

Instruction and Data Cache

The ADSP-SC595/SC596/SC598 processors also include a

traditional instruction cache (I-cache) and two data caches

(D-caches, one each for PM/DM) with parity support for all

caches. These caches support one instruction access and two

data accesses over the DM and PM buses per CCLK cycle. The

cache controllers automatically manage the configured L1

memory. The system can configure part of the L1 memory for

automatic management by the cache controllers. The sizes of

Figure 3. SHARC+ SIMD Core Block Diagram

SIMD Core

11-STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

PM DATA 64

DM DATA 64

DM ADDRESS 32

DAG1

16 × 32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

PEx

DATA

16 × 40-BIT

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

PEy

DATA

16 × 40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

DAG2

16 × 32

ALU

MULTIPLIER

SHIFTER

DATA

SWAP

SYSTEM

I/F

USTAT

PM ADDRESS 24

PM DATA 48

DEBUG

TRACE

FLAGS

CEC

BTB

CONFLICT

CACHE

IMIF

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