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ADSP-SC596 데이터시트(PDF) 33 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 33 Page - Analog Devices

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ADSP-SC595/SC596/SC598
Preliminary Technical Data
Rev. PrD
|
Page 33 of 134
|
May 2022
HADC0_EOC_DOUT
HADC0 End of Conversion
A
PA_11
HADC0_MUX0
HADC0 MUX0
E
PE_02
HADC0_MUX1
HADC0 MUX1
E
PE_04
HADC0_MUX2
HADC0 MUX2
E
PE_03
HADC0_VIN0
HADC0 Analog Input at Channel 0
Not Muxed
HADC0_VIN0
HADC0_VIN1
HADC0 Analog Input at Channel 1
Not Muxed
HADC0_VIN1
HADC0_VIN2
HADC0 Analog Input at Channel 2
Not Muxed
HADC0_VIN2
HADC0_VIN3
HADC0 Analog Input at Channel 3
Not Muxed
HADC0_VIN3
HADC0_VIN4
HADC0 Analog Input at Channel 4
Not Muxed
HADC0_VIN4
HADC0_VIN5
HADC0 Analog Input at Channel 5
Not Muxed
HADC0_VIN5
HADC0_VIN6
HADC0 Analog Input at Channel 6
Not Muxed
HADC0_VIN6
HADC0_VIN7
HADC0 Analog Input at Channel 7
Not Muxed
HADC0_VIN7
HADC0_VREFN
HADC0 Ground Reference for ADC
Not Muxed
HADC0_VREFN
HADC0_VREFP
HADC0 External Reference for ADC
Not Muxed
HADC0_VREFP
JTG_TCK
JTAG Clock
Not Muxed
JTG_TCK
JTG_TDI
JTAG Serial Data In
Not Muxed
JTG_TDI
JTG_TDO
JTAG Serial Data Out
Not Muxed
JTG_TDO
JTG_TMS
JTAG Mode Select
Not Muxed
JTG_TMS
JTG_TRST
JTAG Reset
Not Muxed
JTG_TRST
LP0_ACK
LP0 Acknowledge
B
PB_04
LP0_CLK
LP0 Clock
B
PB_06
LP0_D0
LP0 Data 0
B
PB_07
LP0_D1
LP0 Data 1
B
PB_08
LP0_D2
LP0 Data 2
B
PB_09
LP0_D3
LP0 Data 3
B
PB_10
LP0_D4
LP0 Data 4
B
PB_11
LP0_D5
LP0 Data 5
B
PB_12
LP0_D6
LP0 Data 6
B
PB_13
LP0_D7
LP0 Data 7
B
PB_14
LP1_ACK
LP1 Acknowledge
B
PB_02
LP1_CLK
LP1 Clock
C
PC_07
LP1_D0
LP1 Data 0
B
PB_15
LP1_D1
LP1 Data 1
C
PC_00
LP1_D2
LP1 Data 2
C
PC_01
LP1_D3
LP1 Data 3
C
PC_02
LP1_D4
LP1 Data 4
C
PC_03
LP1_D5
LP1 Data 5
C
PC_04
LP1_D6
LP1 Data 6
C
PC_05
LP1_D7
LP1 Data 7
C
PC_06
MLB0_CLK
MLB0 Single-Ended Clock
B
PB_02
MLB0_CLKN
MLB0 Differential Clock (–)
Not Muxed
MLB0_CLKN
MLB0_CLKOUT
MLB0 Clock Single-Ended Clock Out
F
PF_05
MLB0_CLKP
MLB0 Differential Clock (+)
Not Muxed
MLB0_CLKP
MLB0_DAT
MLB0 Single-Ended Data
B
PB_00
MLB0_DATN
MLB0 Differential Data (–)
Not Muxed
MLB0_DATN
MLB0_DATP
MLB0 Differential Clock (+)
Not Muxed
MLB0_DATP
MLB0_SIG
MLB0 Single-Ended Signal
B
PB_01
MLB0_SIGN
MLB0 Differential Signal (–)
Not Muxed
MLB0_SIGN
Table 10. ADSP-SC595/SC596/SC598 400-Ball BGA_ED Signal Descriptions (Continued)
Signal Name
Description
Port
Pin Name



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