ADSP-SC596 datasheet(1/134 Pages) AD

부품명	ADSP-SC596

상세설명	SHARC Dual-Core DSP with Arm Cortex-A55

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SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

Preliminary Technical Data

SHARC+ Dual-Core

DSP with Arm Cortex-A55

ADSP-SC595/SC596/SC598

Rev. PrD

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

One Analog Way, Wilmington, MA 01887 U.S.A.

Tel: 781.935.5565

Technical Support

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SYSTEM FEATURES

Dual-enhanced SHARC+ high performance floating-point

cores

Up to 1000 MHz per SHARC+ core

5 Mb (640 kB) L1 SRAM memory per core with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Byte, short word, word, long word addressed

Arm Cortex-A55 core

Up to 1200 MHz/3360 DMIPS with advanced SIMD and

floating-point support

32 kB L1 instruction cache with parity/32 kB L1 data cache

with ECC

256 kB L2 cache with ECC

Powerful DMA system with 8 MemDMAs

On-chip memory protection

Integrated safety features

17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),

RoHS compliant

Low system power across automotive temperature range

MEMORY

Large (up to 2 MB) on-chip L2 SRAM with ECC protection

One L3 interface optimized for low system power, providing

16-bit interface to DDR3/DDR3L (supporting 1.35 V

capable DDR3L devices) devices

ADDITIONAL FEATURES

Security and Protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Supports Arm TrustZone and cryptographic extension

Accelerators

FIR, IIR offload engines

Figure 1. ADSP-SC598 (Full-Featured Model) Processor Block Diagram

SYSTEM

L2 MEMORY

L3 MEMORY

INTERFACE

DDR3/DDR3L

DATA

16

SYSTEM CROSSBAR AND DMA SUBSYSTEM

SRAM

(ECC)

2 MB

SYSTEM CONTROL

SYSTEM PROTECTION UNIT (SPU)

SECURITY AND PROTECTION

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

CORE 1

BOOT ROM

CLOCK GENERATION UNIT (CGU)

CLOCK, RESET, AND POWER

RESET CONTROL UNIT (RCU)

Arm® CoreSight

TM

DEBUG UNIT

CLOCK DISTRIBUTION

UNIT (CDU)

DYNAMIC POWER MANAGEMENT

(DPM)

SYSTEM WATCHPOINT UNIT

(SWU)

TRIGGER ROUTING (TRU)

SYS EVENT CORE 0 (GIC)

PROGRAM FLOW

SYS EVENT CORES 1-2 (SEC)

32 kB L1 I-CACHE

32 kB L1 D-CACHE

L1 CACHE (PARITY/ECC)

L2 CACHE

256 kB (ECC)

CORE 0

(1.2 GHz)

Arm

Cortex-A55

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

CORE 2

FAULT MANAGEMENT UNIT (FMU)

FIR

(1 GHz)

4× IIR

(1 GHz)

ACCELERATORS

®

(1 GHz)

S

(1 GHz)

S

PERIPHERALS

40

SRU

DAI0

DAI1

DRU

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

CRYPTOGRAPHIC HARDWARE

ACCELERATOR

QUAD CRC (WITH MemDMA)

WATCHDOGS

THERMAL MONITOR UNIT (TMU)

OTP MEMORY

Arm® TrustZone® SECURITY AND

CRYPTOGRAPHIC EXTENSION

G

P

I

O

135

2× LINK PORTS

4× UARTs

16× TIMERS + 1× COUNTER

1× EPPI

2× CAN FD

2× EMAC

32x CORE FLAGS I/O

2× SPI + 2× QUAD SPI +

1× OCTAL SPI

6× I

2C

1× USB 2.0 HS OTG

CONTROLLER

MLB 3-PIN

HADC (8-CHANNEL, 12-BIT)

1× eMSI (eMMC)

MLB 6-PIN

FIR

(1 GHz)

4× IIR

(1 GHz)

ACCELERATORS

ASRC

8× PAIRS

8× PRECISION CLOCK

GENERATORS

FULL SPORT

0-7

2× S/PDIF Rx/Tx

2× 4-CHANNEL

PDM MIC INPUT

유사한 부품 번호 - ADSP-SC596

제조업체	부품명	데이터시트	상세설명
Analog Devices	ADSP-SC591	3Mb / 143P	SHARC Dual-Core DSP with Arm Cortex-A5 5/2021-Rev. PrC to Rev. PrD
	ADSP-SC591	3Mb / 145P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. A
	ADSP-SC591BBPZ6	3Mb / 145P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. A
	ADSP-SC591BBPZ8	3Mb / 145P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. A
	ADSP-SC591KBPZ6	3Mb / 145P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. A

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유사한 설명 - ADSP-SC596

제조업체	부품명	데이터시트	상세설명
List of Unclassifed Man...	A10S	1Mb / 82P	ARM Cortex-A8 Core
List of Unclassifed Man...	A13	1Mb / 55P	ARM Cortex A8 Core
Analog Devices	ADSP-SC582	3Mb / 168P	SHARC plus Dual Core DSP with ARM Cortex-A5 Rev. PrF
	ADSP-SC570	3Mb / 142P	SHARC Dual-Core DSP with ARM Cortex-A5 6/2018-Rev. A to Rev. B
	ADSP-21591	3Mb / 143P	SHARC Dual-Core DSP with Arm Cortex-A5 5/2021-Rev. PrC to Rev. PrD
List of Unclassifed Man...	DE10-NANO	7Mb / 118P	Cyclone V SoC with Dual-core ARM Cortex-A9
Analog Devices	ADSP-SC582	3Mb / 173P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. B
Analog Devices	ADSP-21591	3Mb / 145P	SHARC Dual-Core DSP with Arm Cortex-A5 Rev. A
Advantech Co., Ltd.	RSB-4810	584Kb / 2P	Rockchip Arm Cortex-A55 RK3568 3.5 SBC 18-Apr-2022
Rockchip Electronics Co...	RV1108	2Mb / 68P	Single-core ARM Cortex-A7 Core processor Revision 1.4 June. 2018

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ADSP-SC596 데이터시트(PDF) 1 Page - Analog Devices

ADSP-SC596 데이터시트(HTML) 1 Page - Analog Devices

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