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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADSP-SC596 데이터시트(PDF) 67 Page - Analog Devices |
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ADSP-SC596 데이터시트(HTML) 67 Page - Analog Devices |
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67 / 134 page  ADSP-SC595/SC596/SC598 Preliminary Technical Data Rev. PrD | Page 67 of 134 | May 2022 Clock Current The dynamic clock currents provide the total power dissipated by all transistors switching in the clock paths. The power dissi- pated by each clock domain is dependent on voltage (VDD_INT), operating frequency, and a unique scaling factor. IDD_INT_SYSCLK_DYN (mA) = 0.651 × fSYSCLK (MHz) × VDD_INT (V) IDD_INT_SCLK0_DYN (mA) = 0.41 × fSCLK0 (MHz) × VDD_INT (V) IDD_INT_SCLK1_DYN (mA) = 0.015 × fSCLK1 (MHz) × VDD_INT (V) IDD_INT_DCLK_DYN (mA) = 0.097 × fDCLK (MHz) × VDD_INT (V) IDD_INT_OCLK_DYN (mA) = 0.093 × fOCLK (MHz) × VDD_INT (V) Data Transmission Current The data transmission current represents the power dissipated when moving data throughout the system via DMA. This cur- rent is proportional to the data rate. Refer to the power calculator available with Estimating Power for ADSP-SC595/ SC596/SC598 SHARC+ Processors (EE-TBD) to estimate IDD_INT_DMA_DR_DYN based on the bandwidth of the data transfer. HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Table 27. Dynamic Current for SHARC+®Core (mA, with ASF = 1.00) fCCLK (MHz) Voltage (VDD_INT) 0.95 V 1.00 V 1.05 V 400 TBD TBD TBD 450 TBD TBD TBD 500 TBD TBD TBD 550 TBD TBD TBD 600 TBD TBD TBD 650 TBD TBD TBD 700 TBD TBD TBD 750 TBD TBD TBD 800 TBD TBD TBD 850 TBD TBD TBD 900 TBD TBD TBD 950 TBD TBD TBD 1000 TBD TBD TBD Table 28. Dynamic Current for the Arm ® Cortex®-A55 Core (mA, with ASF = 1.00) fCCLK (MHz) Voltage (VDD_INT) 0.95 V 1.00 V 1.05 V TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Table 29. HADC Electrical Characteristics Parameter Conditions Typ Unit IDD_HADC_IDLE Current consumption on VDD_HADC HADC is powered on, but not converting TBD mA IDD_HADC_ACTIVE Current consumption on VDD_HADC during a conversion TBD mA IDD_HADC_POWERDOWN Current consumption on VDD_HADC Analog circuitry of the HADC is powered down TBD μA Table 30. HADC DC Accuracy for BGA_ED1 1 See the Preliminary Operating Conditions section for the HADC0_VINx specification. Parameter Typ Unit2 2 LSB = HADC0_VREFP ÷ 1024. Resolution TBD Bits No Missing Codes (NMC) TBD Bits Integral Nonlinearity (INL) ±TBD LSB Differential Nonlinearity (DNL) ±TBD LSB Offset Error ±TBD LSB Offset Error Matching ±TBD LSB Gain Error ±TBD LSB Gain Error Matching ±TBD LSB Table 31. HADC Timing Specifications Parameter Typ Max Unit Conversion Time1 1 Refer to the ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference for additional information about TSAMPLE. 20 × TSAMPLE μs Throughput Range TBD MSPS TWAKEUP TBD μs |
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