ADSP-SC596 datasheet(25/134 Pages) AD

25 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 25 of 134

May 2022

DMC_VREF[n]

Input

Voltage Reference. Connects to half of the VDD_DMC voltage.

DMC_WE

Output

Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

other DMC command signals. Connect to the WE input of dynamic memory.

EMSI0_CD

Input

EMSI0 Card Detect. Connect to GND when an eMMC device is connected.

EMSI0_CLK

Output

EMSI0 Clock. Clock signal applied to the connected device from the eMSI.

EMSI0_CMD

InOut

EMSI0 Command. Sends commands to and receives responses from the connected device.

EMSI0_D[n]

InOut

Data n. Bidirectional data bus.

EMSI0_RST

Output

EMSI0 Reset. eMMC device reset signal.

EMSI0_WP

Input

EMSI0 Write Protect. Connect to VDD_EXT when an eMMC device is connected.

ETH_COL

Input

MII Collision Detect. Collision detect input signal valid only in MII.

ETH_CRS

Input

MII Carrier Sense. Asserted by the PHY when either the transmit or receive medium is not idle.

Deasserted when both are idle. This signal is not used in RMII/RGMII modes.

ETH_MDC

Output

Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII.

ETH_MDIO

InOut

Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII.

ETH_PHY_INT

Input

PHY Interrupt. This signal can be connected to the interrupt output signal from the PHY. PHY interrupt

inside the EMAC module is generated when a rising edge is detected on this pin.

ETH_PTPAUX_MCG_IN[n] Input

PTP Auxiliary/Media Clock Generation Trigger Input. Assert this signal to take an auxiliary

snapshot of the time and store it in the auxiliary time stamp FIFO or capture the presentation time by

sampling at positive, negative, or both edges of the trigger input when operating in media clock

generation mode. Note that the PTP auxiliary and media clock generation modes are mutually

exclusive.

ETH_PTPCLKIN[n]

Input

PTP Clock Input. Optional external PTP clock input.

ETH_PTPPPS[n]

Output

PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted

based on the PPS mode selected. Otherwise, this signal is asserted every time the seconds counter is

incremented.

ETH_REFCLK

Input

Reference Clock. Externally supplied Ethernet clock.

ETH_RXCLK_REFCLK

Input

RXCLK (10/100/1000) or REFCLK (10/100).

ETH_RXCTL_CRSRX_DV

InOut

RXCTL (10/100/1000) or CRSRX_DV (10/100). In RGMII mode, RXCTL multiplexes receive data valid

and receiver error. In RMII mode, CRSRX_DV is carrier sense and receive data valid (CRS_DV), multi-

plexed on alternating clock cycles. In MII mode, CRSRX_DV is receive data valid (RX_DV), asserted by

the PHY when the data on ETH_RXD[n] is valid.

ETH_RXD[n]

Input

Receive Data n. Receive data bus.

ETH_RXERR

Input

Receive Error.

ETH_TXCLK

Input

Reference Clock. Externally supplied Ethernet clock.

ETH_TXCTL_TXEN

Output

TXCTL (10/100/1000) or TXEN (10/100).

ETH_TXD[n]

Output

Transmit Data n. Transmit data bus.

ETH_TXEN

Output

Transmit Enable. When asserted, this signal indicates the data on ETH_TXD[n] is valid.

HADC_EOC_DOUT

Output

End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the

end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate

bit in HADC_CTL.

HADC_MUX[n]

Output

Controls to External Multiplexer. Allows additional input channels when connected to an external

multiplexer.

HADC_VIN[n]

Input

Analog Input at Channel n. Analog voltage inputs for digital conversion.

HADC_VREFN

Input

Ground Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

HADC_VREFP

Input

External Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

JTG_TCK

Input

JTAG Clock. JTAG test access port clock.

JTG_TDI

Input

JTAG Serial Data In. JTAG test access port data input.

JTG_TDO

Output

JTAG Serial Data Out. JTAG test access port data output.

Table 9. ADSP-SC595/SC596/SC598 Detailed Signal Descriptions (Continued)

Signal Name

Direction Description

ADSP-SC596 데이터시트(PDF) 25 Page - Analog Devices

ADSP-SC596 데이터시트(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL