ADSP-SC596 datasheet(27/134 Pages) AD

27 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 27 of 134

May 2022

SPI_SEL[n]

Output

Slave Select Output n. Used in master mode to enable the desired slave.

SPI_SS

Input

Slave Select Input.

Slave mode—acts as the slave select input.

Master mode—optionally serves as an error detection input for the SPI when there are multiple

masters.

SPT_ACLK

InOut

Channel A Clock. Data and frame sync are driven or sampled with respect to this clock. This signal

can be either internally or externally generated.

SPT_AD0

InOut

Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_AD1

InOut

Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_AFS

InOut

Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_ATDV

Output

Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

SPT_BCLK

InOut

Channel B Clock. Data and frame sync are driven or sampled with respect to this clock. This signal

can be either internally or externally generated.

SPT_BD0

InOut

Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_BD1

InOut

Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_BFS

InOut

Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_BTDV

Output

Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

SYS_BMODE[n]

Input

Boot Mode Control n. Selects the boot mode of the processor.

SYS_CLKIN0

Input

Clock/Crystal Input.

SYS_CLKIN1

Input

Clock/Crystal Input.

SYS_CLKOUT

Output

Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter

of the ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference for more details.

SYS_FAULT

InOut

Active-High Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_FAULT

InOut

Active-Low Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_HWRST

Input

Processor Hardware Reset Control. Resets the device when asserted.

SYS_RESOUT

Output

Reset Output. Indicates the device is in the reset state.

SYS_XTAL0

Output

Crystal Output.

SYS_XTAL1

Output

Crystal Output.

TM_ACI[n]

Input

Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

TM_ACLK[n]

Input

Alternate Clock n. Provides an additional time base for an individual timer.

TM_CLK

Input

Clock. Provides an additional global time base for all GP timers.

TM_TMR[n]

InOut

Timer n. The main input/output signal for each timer.

TRACE_CLK

Output

Trace Clock. Clock output.

TRACE_D[nn]

Output

Trace Data n. Unidirectional data bus.

TWI_SCL

InOut

Serial Clock. Clock output when controller, clock input when target.

TWI_SDA

InOut

Serial Data. Receives or transmits data.

UART_CTS

Input

Clear to Send. Flow control signal.

UART_RTS

Output

Request to Send. Flow control signal.

UART_RX

Input

Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

Table 9. ADSP-SC595/SC596/SC598 Detailed Signal Descriptions (Continued)

Signal Name

Direction Description

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