ADSP-SC596 datasheet(65/134 Pages) AD

65 / 134 page

Rev. PrD

Page 65 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 400 MHz

ASFSHARC =0.35

fSYSCLK =200 MHz

fSCLK0 = 100 MHz

fSCLK1 = 250 MHz

(Other clocks are disabled)

No peripheral or DMA activity

TJ = 25°C

VDD_INT = 1.0 V

TBD

IDD_TYP

VDD_INT Current

fCCLK = 400 MHz

ASFSHARC =1.0

fSYSCLK =200 MHz

fSCLK0 = 100 MHz

fSCLK1 = 250 MHz

(Other clocks are disabled)

DMA data rate = 456 MB/s

TJ = 25°C

VDD_INT = 1.0 V

TBD

IDD_INT

VDD_INT Current

fCCLK 0 MHz

fSCLK0/1  0 MHz

IDD_INT_TOT

See equation in

the Total

Internal Power

Dissipation

section.

1 Applies to all output and bidirectional pins operating at less than or equal to 62.5 MHz, except DMC and SYS_XTAL0.

2 Applies to all output and bidirectional pins operating above 62.5 MHz and less than or equal to 125 MHz, except DMC.

3 Applies to SYS_XTAL0 pin.

4 Applies to all DMC output and bidirectional signals in DDR3L mode.

5 Applies to all DMC output and bidirectional signals in DDR3 mode.

6 Applies to input pins: SYS_BMODE2-0, SYS_CLKIN, and SYS_HWRST.

7 Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK.

8 Applies to JTAG_TRST signal.

9 Applies to signals: PA15 to PA0, PB15 to PB0, PC7 to PC0, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS,

SYS_FAULT, and JTG_TDO.

10Applies to all signal pins.

11See Estimating Power for ADSP-SC595/SC596/SC598 SHARC+ Processors (EE-TBD) for further information.

Parameter

Conditions

Min

Typ

Max

Unit

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