ADSP-SC596 datasheet(16/134 Pages) AD

16 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 16 of 134

May 2022

• Optional packing and unpacking of data to/from 32 bits

from/to 8 bits, 16 bits, and 24 bits. If packing/unpacking is

enabled, configure endianness to change the order of pack-

ing/unpacking of bytes or words.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

• Various deinterleaving/interleaving modes for receiving or

transmitting 4:2:2 YCrCb data

• Configurable LCD data enable output available on Frame

Sync 3

Universal Asynchronous Receiver/Transmitter

(UART) Ports

The processors provide four full-duplex universal asynchronous

receiver/transmitter (UART) ports, fully compatible with PC

standard UARTs. Each UART port provides a simplified UART

interface to other peripherals or hosts, supporting full-duplex,

DMA supported, asynchronous transfers of serial data. A UART

port includes support for five to eight data bits as well as no par-

ity, even parity, or odd parity.

Optionally, an additional address bit can be transferred to inter-

rupt only addressed nodes in multidrop bus (MDB) systems. A

frame is terminated by a configurable number of stop bits.

The UART ports support automatic hardware flow control

through the clear to send (CTS) input and request to send (RTS)

output with programmable assertion first in, first out (FIFO)

levels.

To help support the Local Interconnect Network (LIN) proto-

cols, a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable interframe space.

Serial Peripheral Interface (SPI) Ports

The processors have four industry-standard SPI-compatible

ports that allow the processors to communicate with multiple

SPI-compatible devices.

The baseline SPI peripheral is a synchronous, 4-wire interface

consisting of two data pins, one device select pin, and a gated

clock pin. The two data pins allow full-duplex operation to

other SPI-compatible devices. An extra two (optional) data pins

are provided to support quad-SPI operation. Enhanced modes

of operation, such as flow control, fast mode, and dual-I/O

mode (DIOM), are also supported. DMA mode allows for trans-

ferring several words with minimal central processing unit

(CPU) interaction.

With a range of configurable options, the SPI ports provide a

glueless hardware interface with other SPI-compatible devices

in master mode, slave mode, and multimaster environments.

The SPI peripheral includes programmable baud rates, clock

phase, and clock polarity. The peripheral can operate in a multi-

master environment by interfacing with several other devices,

acting as either a master device or a slave device. In a multimas-

ter environment, the SPI peripheral uses open-drain outputs to

avoid data bus contention. The flow control features enable slow

slave devices to interface with fast master devices by providing

an SPI ready pin (SPI_RDY), which flexibly controls the

transfers.

The baud rate and clock phase and polarities of the SPI port are

programmable. The port has integrated DMA channels for both

transmit and receive data streams.

Octal Serial Peripheral Interface (OSPI) Port

The octal serial peripheral interface (OSPI) port provides an

increased external memory data bus width (up to eight bits in

parallel). The OSPI port supports dual data rate (DDR) modes

of operation, which enable the transfer of up to 16 bits of data

each clock cycle. The OSPI port provides overall data through-

put and performance improvement, including faster boot time.

Features of the OSPI port include:

• Support for single-, dual-, quad-, or octal-I/O transfers

• Multiple modes of operation including direct and software

triggered instruction generator (STIG)

• Support for execute in place (XIP): continuous mode

• Programmable page and block sizes

• Programmable write protected regions

• Programmable memory timing

• Support for DDR commands

• Support for PHY mode of operation to enable high speed

transfers

• Support for DQS to increase robustness of data sampling at

higher speeds

Link Port (LP)

Two 8-bit wide link ports (LPs) can connect to the link ports of

other DSPs or peripherals. Link ports are bidirectional and have

eight data lines, an acknowledge line, and a clock line.

Link ports can operate in reduced pin mode, thereby reducing

the number of pins required to interface between two proces-

sors. For example, two processors can be connected using the

link port in 4-bit single data rate (SDR) and dual data rate

(DDR) modes.

Ethernet Media Access Controller (EMAC)

The processor features an ethernet media access controller

(EMAC): 10/100/1000 AVB Ethernet with precision time proto-

col (IEEE 1588).

The processors can directly connect to a network through

embedded fast EMAC that supports 10Base-T (10 Mb/sec),

100Base-T (100 Mb/sec) and 1000Base-T (1 Gb/sec) operations.

Some standard features of the EMAC are as follows:

• Support of MII/RMII/RGMII protocols for external PHYs

• Full-duplex and half-duplex modes

• Media access management (in half-duplex operation)

• Flow control

• Station management, including the generation of

MDC/MDIO frames for read/write access to PHY registers

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