ADSP-SC596 datasheet(5/134 Pages) AD

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ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 5 of 134

May 2022

ARM CORTEX-A55 PROCESSOR

The Arm Cortex-A55 processor is featured on the ADSP-

SC595/SC596/SC598 processors. This section will be fully popu-

lated in a subsequent revision to this document.

SHARC PROCESSOR

The SHARC processor integrates a SHARC+ SIMD core, L1

memory crossbar, I-cache/D-cache controller, L1 memory

blocks, and the requester/completer ports, as shown in Figure 2.

The SHARC+ SIMD core block diagram is shown in Figure 3.

The SHARC processor supports a modified Harvard architec-

ture in combination with a hierarchical memory structure. L1

memories typically operate at the full processor speed with little

or no latency.

L1 Memory

Figure 4 shows the ADSP-SC595/SC596/SC598 memory map.

Each SHARC+ core has a tightly coupled 5 Mb L1 SRAM. Each

SHARC+ core can access code and data in a single cycle from

this memory space. The Arm Cortex-A55 core can also access

this memory space with multicycle accesses.

In the SHARC+ core private address space, both cores have L1

memory.

SHARC+ core memory-mapped register (CMMR) address

space is 0x00000000 through 0x0003FFFF in normal word

(32-bit). Each block can be configured for different combina-

tions of code and data storage. Of the 5 Mb SRAM, up to 1 Mb

can be configured for data memory (DM), program memory

(PM), and instruction cache. Each memory block supports sin-

gle-cycle, independent accesses by the core processor and I/O

processor. The memory architecture, in combination with its

separate on-chip buses, allows two data transfers from the core

and one from the direct memory access (DMA) engine in a

single cycle.

The SRAM of the processor can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data,

106.7k words of 48-bit instructions (or 40-bit data), or combi-

nations of different word sizes up to 5 Mb. All of the memory

can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.

Support of a 16-bit floating-point storage format doubles the

amount of data that can be stored on chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-point formats is performed in a single instruction. Whereas

each memory block can store combinations of code and data,

Figure 2. SHARC Processor Block Diagram

RAM

I-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

I/O (32)

INTERNAL MEMORY INTERFACE (IMIF)

I-CACHE/D-CACHE CONTROL

SHARC+

SIMD CORE

COMPLETER

PORT 1

CORE

MMR

DM (64)

PM (64)

PS (64/48)

(32)

REQUESTER

PORT INSTRUCTION

REQUESTER

PORT DATA

I/O (32)

CMD (64)

CMI (64)

SYSTEM FABRIC

SYSCLK

DOMAIN

INTERRUPT

SYSTEM

EVENT

CONTROLLER

SIMD Processor

CCLK DOMAIN

COMPLETER

PORT 2

(MDMA AND

ACCELERATORS)

I/O (32)

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