ADSP-SC596 datasheet(13/134 Pages) AD

13 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 13 of 134

May 2022

Trigger Routing Unit (TRU)

The trigger routing unit (TRU) provides system level sequence

control without core intervention. The TRU maps trigger gener-

ators to trigger receivers. Trigger receivers can be configured to

respond to triggers in various ways. Common applications

enabled by the TRU include,

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

• Software triggering

• Synchronization of concurrent activities

SECURITY FEATURES

The following sections describe the security features of the

ADSP-SC595/SC596/SC598 processors.

Arm TrustZone

The ADSP-SC595/SC596/SC598 processors provide TrustZone

technology that is integrated into the Arm Cortex-A55 proces-

sors. The TrustZone technology enables a secure state that is

extended throughout the system fabric.

Cryptographic Hardware Accelerators

The ADSP-SC595/SC596/SC598 processors support standards-

based hardware accelerated encryption, decryption, authentica-

tion, and true random number generation.

Support for the hardware accelerated cryptographic ciphers

includes the following:

• AES in ECB, CBC, ICM, and CTR modes with 128-bit,

192-bit, and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

• ARC4 in stateful, stateless mode, up to 128-bit key

Support for the hardware accelerated hash functions includes

the following:

•SHA-1

• SHA-2 with 224-bit and 256-bit digests

• HMAC transforms for SHA-1 and SHA-2

•MD5

Public key accelerator (PKA) is available to offload computation

intensive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudorandom number generator are available.

Secure boot is also available with 224-bit and 256-bit elliptic

curve digital signatures ensuring integrity and authenticity of

the boot stream. Optionally, ensuring confidentiality through

AES-128 encryption is available.

Employ secure debug to allow only trusted users to access the

system with debug tools.

System Protection Unit (SPU)

The system protection unit (SPU) guards against accidental or

unwanted access to an MMR space of the peripheral by provid-

ing a write protection mechanism. The user can choose and

configure the protected peripherals as well as configure which of

the six system MMR requesters (Arm Cortex-A55, two

SHARC+ cores, two memory DMA, and Arm® CoreSight

debug) the peripherals are guarded against.

The SPU is also part of the security infrastructure. Along with

providing write protection functionality, the SPU is employed

to define which resources in the system are secure or nonsecure

as well as block access to secure resources from nonsecure

requesters.

System Memory Protection Unit (SMPU)

The system memory protection unit (SMPU) provides memory

protection against read and/or write transactions to defined

regions of memory. There are SMPU units in the ADSP-

SC595/SC596/SC598 processors for each memory space, except

for SHARC L1.

The SMPU is also part of the security infrastructure. It allows

the user to protect against arbitrary read and/or write transac-

tions and allows regions of memory to be defined as secure and

prevent nonsecure requesters from accessing those memory

regions.

SECURITY FEATURES DISCLAIMER

Analog Devices does not guarantee that the Security Features

described herein provide absolute security. ACCORDINGLY,

ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL

EXPRESS AND IMPLIED WARRANTIES THAT THE

SECURITY FEATURES CANNOT BE BREACHED,

COMPROMISED, OR OTHERWISE CIRCUMVENTED AND

IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR

ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF

DATA, INFORMATION, PHYSICAL PROPERTY, OR

INTELLECTUAL PROPERTY.

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

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