ADSP-SC596 datasheet(10/134 Pages) AD

10 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 10 of 134

May 2022

SYSTEM MEMORY MAP

Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+

® Addressing Memory Map (Private Address Space)

Memory

Long Word (64 Bits)

Extended Precision/

ISA Code (48 Bits)

Normal Word (32 Bits)

Short Word/

VISA Code (16 Bits)

Byte Access (8 Bits)

L1 Block 0 SRAM

(192 KB)

0x00048000–

0x0004DFFF

0x00090000–

0x00097FFF

0x00090000–

0x0009BFFF

0x00120000–

0x00137FFF

0x00240000–

0x0026FFFF

L1 Block 1 SRAM

(192 KB)

0x00058000–

0x0005DFFF

0x000B0000–

0x000B7FFF

0x000B0000–

0x000BBFFF

0x00160000–

0x00177FFF

0x002C0000–

0x002EFFFF

L1 Block 2 SRAM

(128 KB)

0x00060000–

0x00063FFF

0x000C0000–

0x000C5554

0x000C0000–

0x000C7FFF

0x00180000–

0x0018FFFF

0x00300000–

0x0031FFFF

L1 Block 3 SRAM

(128 KB)

0x00070000–

0x00073FFF

0x000E0000–

0x000E5554

0x000E0000–

0x000E7FFF

0x001C0000–

0x001CFFFF

0x00380000–

0x0039FFFF

Table 3. L2 Memory Addressing Map

Memory

Byte Address Space

Arm Cortex-A55: Data Access

and Instruction Fetch

SHARC+: Data Access

Normal Word Address Space

SHARC+ Data Access

VISA Address Space

SHARC+ Instruction Fetch

ISA Address Space

SHARC+ Instruction Fetch

L2 Boot ROM0

Arm: 0x00000000–0x0000FFFF

0x08080000–0x08083FFF

0x00C20000–0x00C27FFF

0x00520000–0x00522AA9

SHARC+/DMA:

0x20200000–0x2020FFFF

L2 RAM (2 MB)1

1 All L2 RAM blocks are subdivided into 256 KB banks. All models feature 2 MB of L2 SRAM (8 banks) except for the ADSP-SC595 models, which feature 1 MB (4 banks).

See Planned Automotive Production Products, Planned Production Products, and Pre Release Products.

0x20000000–0x201FFFFF

0x08000000–0x0807FFFF

0x00B00000–0x00BFFFFF

0x00580000–0x005D5554

L2 RAM (1 MB)1 0x20100000–0x201FFFFF

0x08040000–0x0807FFFF

0x00B80000–0x00BFFFFF

0x005AAAAB–0x005D5554

L2 Boot ROM1

0x20210000–0x2021FFFF

0x08084000–0x08087FFF

0x00C00000–0x00C07FFF

0x00500000–0x00502AA9

L2 Boot ROM2

0x20220000–0x2022FFFF

0x08088000–0x0808BFFF

0x00C40000–0x00C47FFF

0x00540000–0x00542AA9

Table 4. SHARC+® L1 Memory in Multiprocessor Space

Memory

Block

Byte Address Space

Arm Cortex-A55 and SHARC+

Normal Word Address Space

SHARC+

L1 Memory of SHARC1 in

Multiprocessor Space

Address via

Completer 1 Port

Block 0

0x28240000–0x2826FFFF

0x0A090000–0x0A09BFFF

Block 1

0x282C0000–0x282EFFFF

0x0A0B0000–0x0A0BBFFF

Block 2

0x28300000–0x2831FFFF

0x0A0C0000–0x0A0C7FFF

Block 3

0x28380000–0x2839FFFF

0x0A0E0000–0x0A0E7FFF

L1 Memory of SHARC2 in

Multiprocessor Space

Address via

Completer 1 Port

Block 0

0x28A40000–0x28A6FFFF

0x0A290000–0x0A29BFFF

Block 1

0x28AC0000–0x28AEFFFF

0x0A2B0000–0x0A2BBFFF

Block 2

0x28B00000–0x28B1FFFF

0x0A2C0000–0x0A2C7FFF

Block 3

0x28B80000–0x28B9FFFF

0x0A2E0000–0x0A2E7FFF

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