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ADSP-SC596 데이터시트(PDF) 29 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 29 Page - Analog Devices

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ADSP-SC595/SC596/SC598
Preliminary Technical Data
Rev. PrD
|
Page 29 of 134
|
May 2022
400-BALL BGA_ED SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 10 for the
400-ball BGA_ED package. The columns in this table provide
the following information:
• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, where
applicable.
• The description column provides a descriptive name for
each signal.
• The port column shows whether or not a signal is
multiplexed with other signals on a GPIO port pin.
• The pin name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a GPIO pin).
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio
Interface (DAI) chapter of the ADSP-SC595/SC596/SC598
SHARC+ Processor Hardware Reference for complete
information on the use of the DAI and SRUs.
Table 10. ADSP-SC595/SC596/SC598 400-Ball BGA_ED Signal Descriptions
Signal Name
Description
Port
Pin Name
C1_FLG00
SHARC+ Core 1 FLAGS I/O 0
A
PA_12
C1_FLG01
SHARC+ Core 1 FLAGS I/O 1
H
PH_02
C1_FLG02
SHARC+ Core 1 FLAGS I/O 2
B
PB_03
C1_FLG03
SHARC+ Core 1 FLAGS I/O 3
B
PB_02
C1_FLG04
SHARC+ Core 1 FLAGS I/O 4
I
PI_03
C1_FLG05
SHARC+ Core 1 FLAGS I/O 5
I
PI_04
C1_FLG06
SHARC+ Core 1 FLAGS I/O 6
F
PF_02
C1_FLG07
SHARC+ Core 1 FLAGS I/O 7
F
PF_01
C1_FLG08
SHARC+ Core 1 FLAGS I/O 8
E
PE_12
C1_FLG09
SHARC+ Core 1 FLAGS I/O 9
F
PF_09
C1_FLG10
SHARC+ Core 1 FLAGS I/O 10
F
PF_03
C1_FLG11
SHARC+ Core 1 FLAGS I/O 11
D
PD_03
C1_FLG12
SHARC+ Core 1 FLAGS I/O 12
F
PF_13
C1_FLG13
SHARC+ Core 1 FLAGS I/O 13
F
PF_12
C1_FLG14
SHARC+ Core 1 FLAGS I/O 14
G
PG_09
C1_FLG15
SHARC+ Core 1 FLAGS I/O 15
I
PI_05
C2_FLG00
SHARC+ Core 2 FLAGS I/O 0
I
PI_01
C2_FLG01
SHARC+ Core 2 FLAGS I/O 1
I
PI_02
C2_FLG02
SHARC+ Core 2 FLAGS I/O 2
F
PF_06
C2_FLG03
SHARC+ Core 2 FLAGS I/O 3
F
PF_07
C2_FLG04
SHARC+ Core 2 FLAGS I/O 4
F
PF_10
C2_FLG05
SHARC+ Core 2 FLAGS I/O 5
F
PF_11
C2_FLG06
SHARC+ Core 2 FLAGS I/O 6
G
PG_13
C2_FLG07
SHARC+ Core 2 FLAGS I/O 7
E
PE_11
C2_FLG08
SHARC+ Core 2 FLAGS I/O 8
F
PF_08
C2_FLG09
SHARC+ Core 2 FLAGS I/O 9
D
PD_14
C2_FLG10
SHARC+ Core 2 FLAGS I/O 10
D
PD_02
C2_FLG11
SHARC+ Core 2 FLAGS I/O 11
G
PG_12
C2_FLG12
SHARC+ Core 2 FLAGS I/O 12
F
PF_14
C2_FLG13
SHARC+ Core 2 FLAGS I/O 13
E
PE_13
C2_FLG14
SHARC+ Core 2 FLAGS I/O 14
G
PG_10
C2_FLG15
SHARC+ Core 2 FLAGS I/O 15
G
PG_11
CANFD0_RX
CANFD0 Receive
F
PF_15
CANFD0_TX
CANFD0 Transmit
G
PG_00
CANFD1_RX
CANFD1 Receive
G
PG_01
CANFD1_TX
CANFD1 Transmit
G
PG_02



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