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ADSP-SC596 데이터시트(PDF) 86 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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ADSP-SC596 데이터시트(HTML) 86 Page - Analog Devices

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Rev. PrD
|
Page 86 of 134
|
May 2022
ADSP-SC595/SC596/SC598
Preliminary Technical Data
SPI Port—Slave Timing
SPI0, SPI1, and SPI2
Table 51 and Figure 21 describe SPI port slave operations. Note that
• In dual-mode data transmit, the SPIx_MOSI signal is also an output.
• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MISO signal is also an input.
• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT:
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 51. SPI Port—Slave Timing1
1 All specifications apply to SPI0, SPI1, and SPI2.
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
SPIx_CLK High Period2
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external
SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 22.
0.5 × tSPICLKEXT – 1.5
ns
tSPICLS
SPIx_CLK Low Period2
0.5 × tSPICLKEXT – 1.5
ns
tSPICLK
SPIx_CLK Period2
tSPICLKEXT – 1.5
ns
tHDS
Last SPIx_CLK Edge to SPIx_SS Not Asserted
5
ns
tSPITDS
Sequential Transfer Delay
tSPICLKEXT – 1.5
ns
tSDSCI
SPIx_SS Assertion to First SPIx_CLK Edge
11.7
ns
tSSPID
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
2
ns
tHSPID
SPIx_CLK Sampling Edge to Data Input Invalid
1.6
ns
Switching Characteristics
tDSOE
SPIx_SS Assertion to Data Out Active
0
14.12
ns
tDSDHI
SPIx_SS Deassertion to Data High Impedance
0
12.6
ns
tDDSPID
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
14.16
ns
tHDSPID
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
1.5
ns
tSPICLKEXT
1
fSPICLKEXT
----------------
=



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