ADSP-SC596 datasheet(84/134 Pages) AD

84 / 134 page

Rev. PrD

Page 84 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

SPI Port—Master Timing

SPI0, SPI1, and SPI2

Table 50 and Figure 20 describe the SPI port master operations.

When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:

where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65,535.

Note that

• In dual-mode data transmit, the SPIx_MISO signal is also an output.

• In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs.

• In dual-mode data receive, the SPIx_MOSI signal is also an input.

• In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs.

• Quad mode is supported by SPI1 and SPI2.

• CPHA is a configuration bit in the SPI_CTL register.

Table 50. SPI Port—Master Timing1

1 All specifications apply to SPI0, SPI1, and SPI2.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSSPIDM

Data Input Valid to SPIx_CLK Edge (Data Input Setup)

3.5

tHSPIDM

SPIx_CLK Sampling Edge to Data Input Invalid

Switching Characteristics

tSDSCIM

SPIx_SEL Low to First SPI_CLK Edge for CPHA = 12

2 Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1.

tSPICLKPROG – 5

SPIx_SEL Low to First SPI_CLK Edge for CPHA = 02

1.5 × tSPICLKPROG – 5

tSPICHM

SPIx_CLK High Period3

3 See Table 22 for details on the minimum period that can be programmed for tSPICLKPROG.

0.5 × tSPICLKPROG – 1.5

tSPICLM

SPIx_CLK Low Period3

0.5 × tSPICLKPROG – 1.5

tSPICLK

SPIx_CLK Period3

tSPICLKPROG – 1.5

tHDSM

Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 12

1.5 × tSPICLKPROG – 5

Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02

tSPICLKPROG – 5

tSPITDM

Sequential Transfer Delay2, 4

4 Applies to sequential mode with STOP ≥ 1.

tSPICLKPROG – 1.5

tDDSPIDM

SPIx_CLK Edge to Data Out Valid (Data Out Delay)

2.7

tHDSPIDM

SPIx_CLK Edge to Data Out Invalid (Data Out Hold)

–3.75

fSPICLKPROG

fCDU_CLKO6

BAUD



----------------------

tSPICLKPROG

fSPICLKPROG

--------------------

ADSP-SC596 데이터시트(PDF) 84 Page - Analog Devices

ADSP-SC596 데이터시트(HTML) 84 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL