ADSP-SC596 datasheet(18/134 Pages) AD

18 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 18 of 134

May 2022

other peripherals via the TRU (for instance, to signal a fault).

Each timer can also be started and stopped by any trigger gener-

ator without core intervention.

Watchdog Timer (WDT)

Three on-chip software watchdog timers (WDT) can be used by

the Arm Cortex-A55 and/or SHARC+ cores. A software watch-

dog can improve system availability by forcing the processors to

a known state, via a general-purpose interrupt, or a fault, if the

timer expires before being reset by software.

The programmer initializes the count value of the timer, enables

the appropriate interrupt, then enables the timer. Thereafter,

the software must reload the counter before it counts down to

zero from the programmed value, protecting the system from

remaining in an unknown state where software that normally

resets the timer stops running due to an external noise condi-

tion or software error.

General-Purpose Counters (CNT)

A 32-bit general-purpose counter (CNT) is provided that can

operate in general-purpose up/down count modes and can

sense 2-bit quadrature or binary codes as typically emitted by

industrial drives or manual thumbwheels. Count direction is

controlled by a level-sensitive input pin or by two edge

detectors.

A third counter input can provide flexible zero marker support

and can input the push button signal of thumbwheel devices. All

three CNT0 pins have a programmable debouncing circuit.

Internal signals forwarded to a GP timer enable the timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

Housekeeping Analog-to-Digital Converter (HADC)

The housekeeping analog-to-digital converter (HADC) pro-

vides a general-purpose, multichannel, successive

approximation ADC. The following baseline HADC features

apply to all models:

• 12-bit ADC core with built in sample and hold

• Throughput rates up to 1 MSPS

• Single external reference with analog inputs between

0 V and 1.8 V

• Selectable ADC clock frequency including the ability to

program a prescaler

• Adaptable conversion type; allows single or continuous

conversion with option of autoscan

• Total of eight single-ended input channels that can be fur-

ther extended to 15 channels by connecting the

HADC_MUX_PIN_NAME pin(s) to an external channel

multiplexer

• Autosequencing capability with up to a total of eight auto-

conversions in a single session. Each conversion can be

programmed to select one to fifteen input channels.

• 16 data registers (individually addressable) to store conver-

sion values

USB 2.0 High Speed (HS) On the Go (OTG) Controller

The USB supports high speed/full speed/low speed (HS/FS/LS)

USB2.0 on the go (OTG) and UTMI+ low pin interface (USBC).

The USB 2.0 OTG dual-role device controller provides a low

cost connectivity solution in industrial applications, as well as

consumer mobile devices such as cell phones, digital still

cameras, and MP3 players. The USB 2.0 controller allows these

devices to transfer data using a point to point USB connection

without the need for a PC host. The module can operate in a tra-

ditional USB peripheral only mode as well as the host mode

presented in the OTG supplement to the USB 2.0 specification.

The USB controller does not have an integrated on-chip PHY

and must connect to an external PHY on the board through an

USBC 8-bit interface supported by the USB controller.

Media Local Bus (MediaLB)

The automotive model has a Microchip MediaLB (MLB) device

interface that allows the processors to function as a media local

bus device. It includes support for both 3-pin and 6-pin media

local bus protocols. The MLB 3-pin configuration supports

speeds up to 1024 × FS. The MLB 6-pin configuration supports

speed of 2048 × FS. The MLB also supports up to 64 logical

channels with up to 468 bytes of data per MLB frame.

The MLB interface supports MOST25, MOST50, and MOST150

data rates and operates in device mode only.

2-Wire Controller Interface (TWI)

The processors include six 2-wire interface (TWI) modules that

provide a simple exchange method of control data between mul-

tiple devices. The TWI module is compatible with the widely

used I2C bus standard. The TWI module offers the capabilities

of simultaneous controller and target operation and support for

both 7-bit addressing and multimedia data arbitration. The

TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400 kbps. The TWI interface pins are compatible

with 3.3 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulating the port control, status, and interrupt registers:

• The GPIO direction control register specifies the direction

of each individual GPIO pin as input or output.

• GPIO control and status registers have a write-one-to-

modify mechanism that allows any combination of individ-

ual GPIO pins to be modified in a single instruction,

without affecting the level of any other GPIO pins.

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