ADSP-SC596 datasheet(9/134 Pages) AD

9 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 9 of 134

May 2022

Addressing Spaces

In addition to traditionally supported long word, normal word,

extended precision word, and short word addressing aliases, the

processors support byte addressing for the data and instruction

accesses. The enhanced ISA/VISA provides new instructions for

accessing all sizes of data from byte space, as well as converting

word addresses to byte addresses and byte addresses to word

addresses.

SHARC Fabric

The FIR/IIR accelerators on the ADSP-SC595/SC596/SC598

processors are integrated closely with the SHARC+ core with

the help of a dedicated SHARC fabric and run at CCLK speed.

This allows the FIR/IIR accelerator requester ports to directly

access the SHARC L1 memory with reduced latency, as these

accesses do not go through the main system fabric. These

accesses are arbitrated between both the SHARC+ core com-

pleter ports. The SHARC+ core can also access the FIR/IIR

accelerator MMR registers directly.

Additional Features

The enhanced ISA/VISA of the ADSP-SC595/SC596/SC598

processors provides a memory barrier instruction for data syn-

chronization, exclusive data access support for multicore data

sharing, and exclusive data access to enable multiprocessor pro-

gramming. To enhance the reliability of the application, L1 data

RAMs support parity error detection for every byte, and illegal

opcodes are also detected (core interrupts flag both errors).

Requester ports of the core also detect failed external accesses.

SYSTEM INFRASTRUCTURE

The following sections describe the system infrastructure of the

ADSP-SC595/SC596/SC598 processors.

System L2 Memory

A system L2 SRAM memory of up to 16 Mb (2 MB) is available

to both SHARC+ cores, the Arm Cortex-A55 core, and the sys-

tem DMA channels (see Table 3). The L2 SRAM block is

subdivided into up to eight banks to support concurrent access

to the L2 memory ports. Memory accesses to the L2 memory

space are multicycle accesses by both the Arm Cortex-A55 and

SHARC+ cores.

The memory space is used for various situations including

• Arm Cortex-A55 to SHARC+ core data sharing and

intercore communications

• Accelerator and peripheral sources and destination mem-

ory to avoid accessing data in the external memory

• A location for DMA descriptors

• Storage for additional data for either the Arm Cortex-A55

or SHARC+ cores to avoid external memory latencies and

reduce external memory bandwidth

• Storage for incoming Ethernet traffic to improve

performance

• Storage for data coefficient tables cached by the

SHARC+ core

See the System Memory Protection Unit (SMPU) section for

options in limiting access by specific cores and DMA requesters.

The Arm Cortex-A55 core has an L1 instruction and data cache,

each of which is 32 kB in size. The core also has an L2 cache

controller of 256 kB. When enabling the caches, accesses to all

other memory spaces (internal and external) go through the

cache.

SHARC+ Core L1 Memory in Multiprocessor Space

The Arm Cortex-A55 core can access the L1 memory of the

SHARC+ core. See Table 4 for the L1 memory address in multi-

processor space. The SHARC+ core can access the L1 memory

of the other SHARC+ core in the multiprocessor space.

One Time Programmable Memory (OTP)

The processors feature 7 kb of one time programmable (OTP)

memory that is memory-map accessible. This memory can be

programmed with custom keys and supports secure boot and

secure operation.

I/O Memory Space

Mapped I/Os include SPI2/OSPI0 memory address space (see

Table 5).

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