ADSP-SC596 datasheet(62/134 Pages) AD

62 / 134 page

Rev. PrD

Page 62 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

fTMRCLKEXT

External Timer Clock (TMx_CLK)

fTMRCLKEXT ≤ fSCLK0/4

31.25

MHz

fBCLK

Bit Clock Input to PDM

24.576

MHz

fPDM_CLK

PDM Output Clock

6.144

MHz

fUSBC0_CLK

Input Clock From External USB PHY

MHz

1 When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for 3-pin mode and for all supported speeds.

2 To ensure proper operation of the DDR3/3L, all the DDR3/3L guidelines must be strictly followed. See ADSP-SC595/SC596/SC598 Board Design Guidelines for Dynamic

Memory Controller (EE-TBD).

3 fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT.

4 SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due

to the dependency on these factors, the measured jitter may be higher or lower than this typical specification for each end application.

5 The value in the Typ field is the percentage of the SYS_CLKOUT period.

6 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications

section for that peripheral.

7 The peripheral external clock frequency must also be less than or equal to the frequency that clocks the peripheral.

Table 23. Preliminary Phase-Locked Loop (PLL) Operating Conditions

Parameter

Min

Max

Unit

fPLLCLK

PLL Clock Frequency

1.20

2.00

GHz

Figure 6. Clock Relationships and Divider Values

Table 22. Preliminary Clock Operating Conditions (Continued)

Parameter

Conditions

Min

Typ

Max

Unit

SYS_CLKIN

PLL

DCLK

SYSCLK

CCLK OR ARMCCLK

CSEL

SYSSEL

DSEL

OUTCLK

OSEL

PLLCLK

SCLK1

S1SELEXEN

S1SEL

S1SELEX

REFER TO THE ADSP-SC595/SC596/SC598 SHARC+ PROCESSOR HARDWARE REFERENCE

FOR INFORMATION ABOUT ALLOWED DIVIDER VALUES AND PROGRAMMING MODELS.

÷ 2

VCO

ARMCCLK

SCLK0

S0SELEXEN

S0SEL

S0SELEX

÷ 3

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