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ADSP-SC596 데이터시트(PDF) 48 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 48 Page - Analog Devices

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ADSP-SC595/SC596/SC598
Preliminary Technical Data
Rev. PrD
|
Page 48 of 134
|
May 2022
DMC0_DQ15
InOut
B
Internal logic
ensures that input
signal does not float
None
None
VDD_DMC Desc: DMC0 Data 15
Notes: No notes
DMC0_LDM
Output B
None
None
L
VDD_DMC Desc: DMC0 Data Mask for Lower Byte
Notes: No notes
DMC0_LDQS
InOut
C
Internal logic
ensures that input
signal does not float
None
None
VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
Notes: No notes
DMC0_LDQS
InOut
C
Internal logic
ensures that input
signal does not float
None
None
VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
(complement)
Notes: No notes
DMC0_ODT
Output B
None
None
L
VDD_DMC Desc: DMC0 On-Die Termination
Notes: No notes
DMC0_RAS
Output B
None
None
L
VDD_DMC Desc: DMC0 Row Address Strobe
Notes: No notes
DMC0_RESET
Output B
None
None
L
VDD_DMC Desc: DMC0 Reset
Notes: No notes
DMC0_RZQ
a
B
None
None
None
VDD_DMC Desc: DMC0 External Calibration Resistor
Connection
Notes: 34 Ω external pull-down must be
added
DMC0_UDM
Output B
None
None
L
VDD_DMC Desc: DMC0 Data Mask for Upper Byte
Notes: No notes
DMC0_UDQS
InOut
C
Internal logic
ensures that input
signal does not float
None
None
VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
Notes: No notes
DMC0_UDQS
InOut
C
Internal logic
ensures that input
signal does not float
None
None
VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
(complement)
Notes: No notes
DMC0_VREF0
a
None
None
None
VDD_DMC Desc: DMC0 Voltage Reference
Notes: No notes
DMC0_VREF1
a
None
None
None
VDD_DMC Desc: DMC0 Voltage Reference
Notes: No notes
DMC0_WE
Output B
None
None
L
VDD_DMC Desc: DMC0 Write Enable
Notes: No notes
GND
g
None
None
None
Desc: Ground
Notes: No notes
HADC0_VIN0
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 0
Notes: Connect to GND if not used
HADC0_VIN1
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 1
Notes: Connect to GND if not used
HADC0_VIN2
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 2
Notes: Connect to GND if not used
HADC0_VIN3
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 3
Notes: Connect to GND if not used
HADC0_VIN4
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 4
Notes: Connect to GND if not used
HADC0_VIN5
a
NA
None
None
None
VDD_ANA Desc: HADC0 Analog Input 5
Notes: Connect to GND if not used
Table 21. ADSP-SC595/SC596/SC598 Designer Quick Reference (Continued)
Signal Name
Type
Driver
Type
Internal
Termination
Reset
Termination
Reset
Drive
Power
Domain
Description and Notes



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