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ADSP-SC596 데이터시트(PDF) 81 Page - Analog Devices

부품명 ADSP-SC596
상세설명  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 데이터시트(HTML) 81 Page - Analog Devices

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Rev. PrD
|
Page 81 of 134
|
May 2022
ADSP-SC595/SC596/SC598
Preliminary Technical Data
Table 47. SPORTs—External Late Frame Sync1
All specifications are based on simulation data and are subject to change without notice.
Parameter
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay From Late External Transmit Frame Sync or External Receive Frame
Sync With SPORT_MCTL_A/B bits MCE = 1, MFD = 02
14
ns
tDDTENFS
Data Enable for SPORT_MCTL_A/B bits MCE = 1, MFD = 02
0.5
ns
1 Specifications apply to all four SPORTs.
2 The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0.
Figure 17. External Late Frame Sync
DRIVE
SAMPLE
2ND BIT
1ST BIT
DRIVE
tDDTE/I
tHDTE/I
tDDTLFSE
tDDTENFS
tSFSE/I
tHFSE/I
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BCLK
(SPORT CLOCK)



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