ADSP-SC596 datasheet(14/134 Pages) AD

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ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 14 of 134

May 2022

SAFETY FEATURES

The ADSP-SC595/SC596/SC598 processors are designed to

support functional safety applications. Whereas the level of

safety is mainly dominated by the system concept, the following

primitives are provided by the processors to build a robust

safety concept.

Multiparity Bit Protected SHARC+ Core L1 Memories

In the SHARC+ core L1 memory space, whether SRAM or

cache, multiple parity bits protect each word to detect the single

event upsets that occur in all RAMs. Parity also protects the

cache tags and BTB.

Error Correcting Code (ECC) Protected L2 Memories

Error correcting code (ECC) corrects single event upsets. A sin-

gle error correct/double error detect (SEC/DED) code protects

the L2 memory. By default, ECC is enabled, but it can be dis-

abled on a per bank basis. Single-bit errors correct

transparently. If enabled, dual-bit errors can issue a system

event or fault. ECC protection is fully transparent to the user,

even if L2 memory is read or written by 8-bit or 16-bit entities.

ECC and Parity Protected Arm L1/L2 Cache

The Arm Cortex-A55 core cache memory protection scheme

features 1-bit error detection in the L1 instruction cache, as well

as 2-bit error detection and 1-bit error correction in both the L1

data cache and L2 cache. Additionally, the corresponding cache

tags are parity-protected.

Parity and ECC Protected Peripheral Memories

Parity protection is added to the following peripheral memories:

•ASRC

• IIR

•FIR

•USB

•CRYPTO

• EMAC

•MLB

•TRACE

CAN FD memory is ECC protected.

Cyclic Redundancy Check (CRC) Protected Memories

Whereas parity bit and ECC protection mainly protect against

random soft errors in L1 and L2 memory cells, the CRC engines

can protect against systematic errors (pointer errors) and static

content (instruction code) of L1, L2, and even Level 3 (L3)

memories (DDR3, DDR3L). The processors feature four CRC

engines that are embedded in the memory to memory DMA

controllers.

CRC checksums can be calculated or compared automatically

during memory transfers. Alternatively, single or multiple

memory regions can be continuously scrubbed by a single DMA

work unit as per DMA descriptor chain instructions. The CRC

engine also protects data loaded during the boot process.

Signal Watchdogs

The 16 general-purpose (GP) timers feature modes to monitor

off-chip signals. The watchdog period mode monitors whether

external signals toggle with a period within an expected range.

The watchdog width mode monitors whether the pulse widths

of external signals are within an expected range. Both modes

help detect undesired toggling or lack of toggling of system level

signals.

System Event Controller (SEC)

Besides system events, the system event controller (SEC) further

supports fault management, including fault action configura-

tion as timeout, internal indication by system interrupt, or

external indication through the SYS_FAULT pin and system

reset.

Memory Error Controller (MEC)

The memory error controller (MEC) manages memory par-

ity/ECC errors and warnings from the cores and peripherals

and sends out interrupts and triggers.

PROCESSOR PERIPHERALS

The following sections describe the peripherals of the ADSP-

SC595/SC596/SC598 processors.

Dynamic Memory Controller (DMC)

The 16-bit dynamic memory controller (DMC) interfaces to

• DDR3 (JESD79-3), 512 Mb to 8 Gb

• DDR3L (JESD79-3-1A), 512 Mb to 8 Gb

See Table 6 for the DMC memory map.

Digital Audio Interface (DAI)

The processors support two identical digital audio interface

(DAI) units. The DAI can connect various peripherals to any of

the DAI pins.

The application code makes these connections using the signal

routing unit (SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by each DAI instance to inter-

connect under software control. This functionality allows easy

use of the DAI associated peripherals for a wider variety of

applications by using a larger set of algorithms than is possible

with nonconfigurable signal paths.

The DAI includes the peripherals described in the following

sections (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffer 20

and DAI Pin Buffer 19 can change the polarity of the input

signals.

The DAI_PINx pin buffers can also be used as GPIO pins. DAI

input signals allow the triggering of interrupts on the rising

edge, falling edge, or both.

See the Digital Audio Interface (DAI) chapter of the ADSP-

SC595/SC596/SC598 SHARC+ Processor Hardware Reference

for complete information on the use of the DAIs and SRUs.

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