ADSP-SC596 datasheet(8/134 Pages) AD

8 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 8 of 134

May 2022

Core Timer

Each SHARC+ processor core includes an extra timer. This

extra timer is clocked by the internal processor clock and is typ-

ically used as a system tick clock for generating periodic

operating system interrupts.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register register files (16 primary, 16 secondary),

combined with the enhanced Harvard architecture of the pro-

cessor, allow unconstrained data flow between computation

units and internal memory. The registers in the PEx data regis-

ter file are referred to as R0–R15 and in the PEy data register file

as S0–S15.

Context Switch

Many of the registers of the processor have secondary registers

that can activate during interrupt servicing for a fast context

switch. The data, DAG, and multiplier result registers have sec-

ondary registers. The primary registers are active at reset,

whereas control bits in MODE1 activate the secondary registers.

Universal Registers

General-purpose tasks use the universal registers. The four uni-

versal status (USTAT) registers allow easy bit manipulations

(set, clear, toggle, test, XOR) for all control and status peripheral

registers.

The data bus exchange register (PX) permits data to pass

between the 64-bit PM data bus and the 64-bit DM data bus or

between the 40-bit register file and the PM or DM data bus.

These registers contain hardware to handle the data width

difference.

Data Address Generators (DAG) With Zero Overhead

Hardware Circular Buffer Support

For indirect addressing and implementing circular data buffers

in hardware, the ADSP-SC595/SC596/SC598 processors use two

data address generators (DAGs). Circular buffers allow efficient

programming of delay lines and other data structures required

in digital signal processing and are commonly used in digital fil-

ters and fast Fourier transforms (FFT). The DAGs contain

sufficient registers to allow the creation of up to 32 circular buf-

fers (16 primary register sets and 16 secondary sets). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Flexible Instruction Set Architecture (ISA)

The flexible instruction set architecture (ISA), a 48-bit instruc-

tion word, accommodates various parallel operations for

concise programming. For example, the processors can condi-

tionally execute a multiply, an add, and a subtract in both

processing elements while branching and fetching up to four

32-bit values from memory—all in a single instruction.

Additionally, the double-precision floating-point instruction set

is new to the SHARC+ core, as compared with the previous

SHARC core.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC core processors, the SHARC+ core processors

support 16-bit and 32-bit opcodes for many instructions, for-

merly 48-bit in the ISA. This variable instruction set

architecture (VISA) feature drops redundant or unused bits

within the 48-bit instruction to create more efficient and com-

pact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

memories. VISA is not an operating mode; rather, it is address

dependent (refer to the ISA/VISA address spaces in Table 5).

Finally, the processor allows jumps between ISA and VISA

instruction fetches.

Single-Cycle Fetch of Instructional Four Operands

The ADSP-SC595/SC596/SC598 processors feature an

enhanced Harvard architecture in which the DM bus transfers

data and the PM bus transfers both instructions and data.

With the separate program memory bus, data memory buses,

and on-chip instruction conflict cache, the processor can simul-

taneously fetch four operands (two over each data bus) and one

instruction from the conflict cache in a single cycle.

Core Event Controller (CEC)

The SHARC+ core event controller (CEC) can be configured to

service various interrupts generated by the core (including

arithmetic and circular buffer instruction flow exceptions) and

system event controller (SEC) events (peripheral interrupt

request, debug or monitor, and software-raised), responding

only to interrupts enabled in the IMASK register. The output of

the SEC is forwarded to the CEC to respond directly to any

enabled system interrupts. For all SEC channels, the processor

automatically stacks the arithmetic status (ASTATx and

ASTATy) registers and mode (MODE1) register in parallel with

interrupt servicing.

Instruction Conflict Cache

The processors include a 32-entry instruction cache that enables

three-bus operation for fetching an instruction and four data

values. The cache is selective—only the instructions that require

fetches conflict with the PM bus data access cache. This cache

allows full speed execution of core looped operations, such as

digital filter multiply accumulates and FFT butterfly processing.

The conflict cache serves for on-chip bus conflicts only.

Branch Target Buffer (BTB)/Branch Predictor (BP)

Implementation of a hardware-based branch predictor (BP) and

branch target buffer (BTB) reduce branch delay. The program

sequencer supports efficient branching using the BTB for condi-

tional and unconditional instructions.

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