ADSP-SC596 datasheet(70/134 Pages) AD

70 / 134 page

Rev. PrD

Page 70 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Clock and Reset Timing

Table 38 and Figure 9 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLKx, DCLK, and

OCLK timing specifications in Table 22 (Preliminary Clock Operating Conditions), combinations of SYS_CLKIN0 and clock multipliers

must not select clock rates in excess of the maximum instruction rate of the processor.

Dynamic Memory Controller (DMC)—Clock, Control, Write and Read Cycle Timing

The DMC clock, control, write and read timings comply with the JEDEC standards. To ensure proper operation of the DDR3/3L, all

DDR3/3L guidelines must be strictly followed. See ADSP-SC595/SC596/SC598 Board Design Guidelines for Dynamic Memory Controller

(EE-TBD).

Table 38. Clock and Reset Timing

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

SYS_CLKIN0 Frequency (Crystal)1, 2

1 Applies to PLL bypass mode and PLL nonbypass mode.

2 The tCKIN period (see Figure 9) equals 1/fCKIN.

MHz

SYS_CLKIN0 Frequency (External SYS_CLKIN0)1, 2

MHz

tCKINL

SYS_CLKIN0 Low Pulse1

16.67

tCKINH

SYS_CLKIN0 High Pulse1

16.67

tWRST

RESET Asserted Pulse Width Low3

3 Applies after power-up sequence is complete. See Table 37 and Figure 7 for power-up reset timing.

11 × tCKIN

Figure 9. Clock and Reset Timing

SYS_CLKIN0

tWRST

tCKIN

tCKINL

tCKINH

SYS_HWRST

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